HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 291

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

9.11.2 Register Descriptions
Table 9-18 summarizes the registers of port A.
Table 9-18 Port A Registers
Address*
H'FFD1
H'FFD3
Note: * Lower 16 bits of the address.
Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select
input or output for each pin in port A. When pins are used for TPC output, the corresponding
PADDR bits must also be set.
A pin in port A becomes an output pin if the corresponding PADDR bit is set to 1, and an input
pin if this bit is cleared to 0. In modes 3, 4, and 6, PA
address output pin.
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 by a reset and in hardware standby mode in modes 1, 2, 5, and 7.
It is initialized to H'80 by a reset and in hardware standby mode in modes 3, 4, and 6. In software
standby mode it retains its previous setting. If a PADDR bit is set to 1, the corresponding pin
maintains its output state in software standby mode.
Bit
Modes
3, 4,
and 6
Modes
1, 2, 5,
and 7
Initial value
Read/Write
Initial value
Read/Write
Name
Port A data direction
register
Port A data register
PA DDR
7
—
W
7
1
0
PA DDR
6
W
W
6
0
0
PADDR
PADR
Abbre-
viation
PA DDR
5
W
W
5
0
0
Port A data direction 7 to 0
These bits select input or output for port A pins
278
R/W
W
R/W
PA DDR
4
W
W
4
0
0
7
DDR is fixed at 1 and PA
Modes 1, 2, 5 and 7
H'00
H'00
PA DDR
3
W
W
3
0
0
PA DDR
2
W
W
2
0
0
Initial Value
PA DDR
7
Modes 3, 4, and 6
H'80
H'00
1
W
W
functions as an
1
0
0
PA DDR
0
W
W
0
0
0