HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 651
HD6433044
Manufacturer Part Number
HD6433044
Description
(HD64 Series) Hitachi Single-Chip Microcomputer
Manufacturer
Hitachi Semiconductor
Datasheet
1.HD6433044.pdf
(867 pages)
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Table 20-1 Power-Down State and Module Standby Function
Mode
Sleep
mode
Software SLEEP instruc- Halted
standby
mode
Hardware Low input at
standby
mode
Module
standby
Notes: 1. RTCNT and bits 7 and 6 of RTMCSR are initialized. Other bits and registers hold their previous states.
Legend
SYSCR: System control register
SSBY:
MSTCR: Module standby control register
2. State in which the corresponding MSTCR bit was set to 1. For details see section 20.2.2, Module Standby Control Register (MSTCR).
3. The RAME bit must be cleared to 0 in SYSCR before the transition from the program execution state to hardware standby mode.
4. When a MSTCR bit is set to 1, the registers of the corresponding on-chip supporting module are initialized. To restart the module, first clear the MSTCR bit to 0,
Software standby bit
Entering
Conditions
SLEEP instruc- Active
tion executed
while SSBY = 0
in SYSCR
tion executed
while SSBY = 1
in SYSCR
STBY pin
Corresponding
bit set to 1 in
MSTCR
then set up the module registers again.
Clock
Halted
Active
CPU
Halted
Halted
Halted
Active
CPU
Registers DMAC
Held
Held
Undeter-
mined
—
Active
Halted
and
reset
Halted
and
reset
Halted
and
reset
*2
Refresh
Controller ITU
Active
Halted
and
held
Halted
and
reset
Halted
and
held
*1
*1
*2
Active
Halted
and
reset
Halted
and
reset
Halted
and
reset
*2
SCI0
Active
Halted
and
reset
Halted
and
reset
Halted
and
reset
State
*2
SCI1
Active
Halted
and
reset
Halted
and
reset
Halted
and
reset
*2
A/D
Active
Halted
and
reset
and
reset
Halted
and
reset
Halted
*2
Other
Modules RAM
Active
Halted
and
reset
Halted
and
reset
Active
Held
Held
Held
—
*3
ø clock
output
ø output
High
output
High
impedance impedance • RES
High
impedance
*2
I/O
Ports
Held
Held
High
Exiting
Conditions
• Interrupt
• RES
• STBY
• NMI
• IRQ
• RES
• STBY
• STBY
• STBY
• RES
• Clear MSTCR
bit to 0
0
to IRQ
*4
2
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