HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 228

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

The transfer count is specified as an 8-bit value in ETCRH and ETCRL. The maximum transfer
count is 255, obtained by setting both ETCRH and ETCRL to H'FF.
Transfers can be requested (activated) by compare match/input capture A interrupts from ITU
channels 0 to 3, transmit-data-empty and receive-data-full interrupts from SCI channel 0, and
external request signals.
For the detailed settings see section 8.2.4, Data Transfer Control Registers (DTCR).
Figure 8-7 shows a sample setup procedure for repeat mode.
destination addresses
Set transfer count
Set source and
Repeat mode
Repeat mode
Read DTCR
Set DTCR
Figure 8-7 Repeat Mode Setup Procedure (Example)
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Set the source and destination addresses in MAR
and IOAR. The transfer direction is determined
automatically from the activation source.
Set the transfer count in both ETCRH and ETCRL.
Read DTCR while the DTE bit is cleared to 0.
Set the DTCR bits as follows.
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Select the DMAC activation source with bits
DTS2 to DTS0.
Clear the DTIE bit to 0 and set the RPE bit to 1
to select repeat mode.
Select MAR increment or decrement with the DTID bit.
Select byte size or word size with the DTSZ bit.
Set the DTE bit to 1 to enable the transfer.
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