HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 513
HD6433044
Manufacturer Part Number
HD6433044
Description
(HD64 Series) Hitachi Single-Chip Microcomputer
Manufacturer
Hitachi Semiconductor
Datasheet
1.HD6433044.pdf
(867 pages)
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14.2.3 Serial Mode Register (SMR)
Bit 7 of SMR has a different function in smart card interface mode. The related serial control
register (SCR) changes from bit 1 to bit 0. However, this function does not exist in the flash
memory version.
Bit 7-GSM Mode (GM): Set at 0 when using the regular smart card interface. In GSM mode, set
to 1. When transmission is complete, initially the TEND flag set timing appears followed by clock
output restriction mode. Clock output restriction mode comprises serial control register bit 1 and
bit 0.
Bit 7
GM
0
1
Bits 6 to 0—Operate in the same way as for the normal SCI.
For details, see section 13.2.5, Serial Mode Register (SMR).
Bit
Initial value
Read/Write
Description
Using the regular smart card interface mode
• The TEND flag is set 12.5 etu after the beginning of the start bit
• Clock output on/off control only
Using the GSM mode smart card interface mode
• The TEND flag is set 11.0 etu after the beginning of the start bit
• Clock output on/off and fixed-high/fixed-low control
R/W
GM
7
0
R/W
CHR
6
0
R/W
PR
5
0
R/W
503
O/E
0
4
R/W
STOP
3
0
R/W
MP
2
0
CKS1
R/W
1
0
(Initial value)
CKS0
R/W
0
0
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