HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 75

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

3.4 Operating Mode Descriptions
3.4.1 Mode 1
Ports 1, 2, and 5 function as address pins A
address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least
one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
3.4.2 Mode 2
Ports 1, 2, and 5 function as address pins A
address space. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all
areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits.
3.4.3 Mode 3
Ports 1, 2, and 5 and part of port A function as address pins A
maximum 16-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to
all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to
16 bits. A
(BRCR). (In this mode A
3.4.4 Mode 4
Ports 1, 2, and 5 and part of port A function as address pins A
maximum 16-Mbyte address space. The initial bus mode after a reset is 16 bits, with 16-bit access
to all areas. If all areas are designated for 8-bit access in ABWCR, the bus mode switches to
8 bits. A
used for address output.)
3.4.5 Mode 5
Ports 1, 2, and 5 can function as address pins A
address space, but following a reset they are input ports. To use ports 1, 2, and 5 as an address bus,
the corresponding bits in their data direction registers (P1DDR, P2DDR, and P5DDR) must be set
to 1. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is
designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
3.4.6 Mode 6
Ports 1, 2, and 5 and part of port A function as address pins A
maximum 16-Mbyte address space, but following a reset they are input ports. To use ports 1, 2,
and 5 as an address bus, the corresponding bits in their data direction registers (P1DDR, P2DDR,
and P5DDR) must be set to 1. For A
A
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is
designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
20
is always used for address output.)
23
23
to A
to A
21
21
are valid when 0 is written in bits 7 to 5 of BRCR. (In this mode A
are valid when 0 is written in bits 7 to 5 of the bus release control register
20
is always used for address output.)
23
to A
19
19
21
to A
to A
output, clear bits 7 to 5 of BRCR to 0. (In this mode
19
60
to A
0
0
, permitting access to a maximum 1-Mbyte
, permitting access to a maximum 1-Mbyte
0
, permitting access to a maximum 1-Mbyte
23
23
23
to A
to A
to A
0
0
0
, permitting access to a
, permitting access to a
, permitting access to a
20
is always