MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 1001

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

17.3.1.4
When a PCI error is detected, the appropriate error bit is set in the PCI error detect register. Subsequent
errors set the appropriate error bits in the error detection registers, but relevant information (attributes,
address, and data) is captured only for the first error. The PCI error detect register is a write-1-to-clear type
register. That is, reading from this register occurs normally; however, write operations are different in that
the bits can be cleared but not set. A bit is cleared whenever the register is written, and the data in the
corresponding bit location is a 1. For example, to clear bit 25 and not affect any other bits in the register,
the value 0x0000_0040 is written to the register.
The error bit is set regardless of the state of the corresponding error enable bit in the PCI error enable
register. The error enable bits are used to send or block the error reporting to the interrupt mechanism. The
interrupt can be cleared by writing 0xFFFF_FFFF to the PCI error detect register.
A master-abort condition during a configuration cycle is not necessarily an error. In this case, if relevant,
the master abort error enable can be disabled to prevent the reporting of master-aborts during outbound
configuration cycles. Master-aborts during configuration reads return 0xFFFF_FFFF.
Freescale Semiconductor
16–19 WTT Write transaction type. Transaction type to run if access is a write. The field description differs subject to
20–25
26–31 IWS Inbound window size. Inbound translation window size N which is the encoded 2^(N+1) bytes window
Bits Name
—
PCI Error Management Registers
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
the transaction being targeted to an I/O interface or to local memory.
Following are the transaction type settings for writes to an I/O interface:
0000–0011 Reserved
0100 Write
0101–1111 Reserved
Following are the transaction type settings for writes to local memory:
0000–Reserved
0100 Write, don’t snoop local processor
0101 Write, snoop local processor
0110 Write, allocate L2 cache line
0111 Write, allocate and lock L2 cache line
1000–1111 Reserved
Reserved
size. The smallest window is 4 Kbytes.
000000 Reserved
...
001011 4-Kbyte window size
001100 8-Kbyte window size
...
011111 4-Gbyte window size
100000 8-Gbyte window size
100001 16-Gbyte window size
100010 Reserved
...
111111 Reserved
For configuration and run-time registers, the window size is fixed at
010011 1-Mbyte window size
For register set 0, the window size is limited to 4 Gbytes or smaller.
Table 17-14. PIWAR n Field Descriptions (continued)
Description
PCI Bus Interface
17-23