MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 327

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

9.3.2
The following sections describe the DDR SDRAM controller input and output signals, the meaning of their
different states, and relative timing information for assertion and negation.
9.3.2.1
Table 9-3
Freescale Semiconductor
MDQ[0:63]
Signal
describes the DDR controller memory interface signals.
Detailed Signal Descriptions
Memory Interface Signals
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
I/O
I/O Data bus. Both input and output signals on the DDR memory controller.
O
I
Table 9-3. Memory Interface Signals—Detailed Signal Descriptions
As outputs for the bidirectional data bus, these signals operate as described below.
As inputs for the bidirectional data bus, these signals operate as described below.
Meaning
Meaning
Timing Assertion/Negation—Driven coincident with corresponding data strobes (MDQS) signal.
Timing Assertion/Negation—The DDR SDRAM drives data during a READ transaction.
State
State
Table 9-2. Memory Address Signal Mappings (continued)
Asserted/Negated—Represent the value of data being driven by the DDR memory controller.
High impedance—No READ or WRITE command is in progress; data is not being driven by
Asserted/Negated—Represents the state of data being driven by the external DDR
High impedance—No READ or WRITE command in progress; data is not being driven by the
1
2
Auto-precharge for DDR signaled on A10 when
DDR_SDRAM_CFG[PCHB8] = 0
Auto-precharge for DDR signaled on A8 when
DDR_SDRAM_CFG[PCHB8] = 1
the memory controller or the DRAM.
SDRAMs.
memory controller or the DRAM.
msb
Signal Name
lsb
lsb
(Outputs)
MBA2
MBA1
MBA0
MA0
JEDEC DDR DIMM Signals
Description
(Inputs)
MBA2
MBA1
MBA0
A0
DDR Memory Controller
9-5