MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 932

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
Table 15-164
Table 15-165
15-202
eTSEC Signals
Set source clock divide by 14, for example, to insure that EC_MDC clock speed is not greater than 2.5 MHz.
Set up the MII Mgmt for a read cycle to TBI Control register (write the TBI’s address and Register address),
GTX_CLK125
MDIO
MDC
Sum
describes the shared signals for the RTBI interface.
describes the register initializations required to configure the eTSEC in RTBI mode.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]
MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]
I/O
I/O
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
O
Table 15-165. RTBI Mode Register Initialization Steps
I
MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]
MACCFG2[0000_0000_0000_0000_0111_0010_0000_0101]
The TBI Control register is at offset address 0x0 from TBIPA.
MIIMCFG[0000_0000_0000_0000_0000_0000_0000_0101]
MIIMADD[0000_0000_0000_0000_0001_0000_0000_0000]
ECNTRL[0000_0000_0000_0000_0001_0000_0000_0000]
Read MII Mgmt Indicator register and check for Busy = 0,
TBIPA[0000_0000_0000_0000_0000_0000_0001_0000]
Signals
No. of
This indicates that the eTSEC MII Mgmt bus is idle.
1
1
1
Table 15-164. Shared RTBI Signals
(This example has Statistics Enable = 1)
Assign a Physical address to the TBI,
Setup the MII Mgmt clock speed,
to 02608C:876543, for example.
to 02608C:876543, for example.
Initialize MAC Station Address,
Initialize MAC Station Address,
(I/F Mode = 2, Full Duplex = 1)
GTX_CLK125
GMII Signals
set to 16, for example.
Initialize MACCFG2,
MDIO
MDC
Sum
Initialize ECNTRL,
Clear Soft_Reset,
Set Soft_Reset,
I/O
I/O
O
I
Signals
No. of
1
1
1
Management interface clock
Management interface I/O
Reference clock
Function
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