MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 839

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

15.5.3.8
This section provides detailed descriptions of the registers used to configure the FIFO interface. All of the
registers are 32 bits wide. The ECNTRL[FIFM] bit is set to indicate that data transfers take place over this
interface. Please refer to
protocols available.
15.5.3.8.1
The FIFO Configuration Register configures and enables the 8-bit FIFO interface.
Figure 15-102
Table 15-105
Freescale Semiconductor
Reset
Reset
Offse
20–22
8–15
Bits
0–7
16
17
18
19
W
W
R
R
t
eTSEC1:0x2_4A00; eTSEC3:0x2_6A00
RRX
16
0
0
0
Name
RRX
RXE
RTX
TXE
IPG
—
—
RTX
FIFO Registers
17
describes the fields of the FIFOCFG register.
0
0
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
describes the definition for the FIFOCFG register.
FIFO Configuration Register (FIFOCFG)
Reserved
Minimum inter packet gap. This sets the minimum number of cycles inserted between back-to-back frames
transmitted over the FIFO interface. If CRC is appended to frames, 7 cycles (8-bit mode) of non-payload
data separates packets.
Enable reset of FIFO receive function.
0 Do not reset the FIFO receiver.
1 Reset the FIFO receiver for as long as this bit is set.
Enable reset of FIFO transmit function.
0 Do not reset the FIFO transmitter.
1 Reset the FIFO transmitter for as long as this bit is set.
Enable FIFO receive function.
0 Disable reception over the FIFO interface, ignoring data presented to the signals.
1 Enable normal reception over the FIFO interface.
Enable FIFO transmit function.
0 Disable transmission over the FIFO interface.
1 Enable normal transmission over the FIFO interface.
Reserved.
RXE
18
0
0
TXE
Section 15.6.2, “Connecting to FIFO
19
0
0
—
Figure 15-102. FIFOCFG Register Definition
20
0
0
Table 15-105. FIFOCFG Field Descriptions
—
0
0
22
0
0
LPB
23
0
0
7
RFC
24
0
1
8
Description
TFC
25
0
1
Interfaces,” for details of the signaling
FFC CRCAPP CRCCHK
26
0
0
Enhanced Three-Speed Ethernet Controllers
27
0
0
IPG
28
0
0
Access: Read/Write
—
29
0
0
30
0
0
SIGM
15-109
15
31
0
0