MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 633

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

14.3.1.2.3
Figure 14-4
Table 14-7
Freescale Semiconductor
17–18
20–22
24–28
0–16
Bits
19
23
29
30
31
Offset 0x004 (OR0)
Reset
W
R
BCTLD Buffer control disable. Disables assertion of LBCTL during access to the current memory bank.
Name
EHTR Extended hold time on read accesses. Indicates with TRLX how many cycles are inserted between a read
TRLX Timing relaxed. Works in conjunction with EHTR to extend hold time on read accesses.
0x00C (OR1)
0x014 (OR2)
0x01C (OR3)
XAM
EAD
0
AM
—
—
BI
describes BRn fields for UPM mode.
shows the bit fields for ORn when the corresponding BRn[MSEL] selects a UPM machine.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
UPM address mask. Masks corresponding BR n bits. Masking address bits independently allows external
devices of different size address ranges to be used. Address mask bits can be set or cleared in any order in
the field, allowing a resource to reside in more than one area of the address map.
0
1 The corresponding address bits are used in the comparison with address signals.
Extended address mask. Masks the corresponding XBA bits in the BR n register, effectively extending the
address mask (AM) by 2 bits.
0 LBCTL is asserted upon access to the current memory bank.
1 LBCTL is not asserted upon access to the current memory bank.
Reserved
Burst inhibit. Indicates if this memory bank supports burst accesses.
0 The bank supports burst accesses.
1 The bank does not support burst accesses. The selected UPM executes burst accesses as a series of
Reserved
access from the current bank and the next access.
External address latch delay. Allow extra bus clock cycles when using external address latch (LALE).
0 No additional bus clock cycles (LALE asserted for one bus clock cycle only)
1 Extra bus clock cycles are added (LALE is asserted for the number of bus clock cycles specified by
Option Registers (OR n )—UPM Mode
single accesses.
LCRR[EADC]).
Corresponding address bits are masked.
TRLX
0
0
1
1
0x024 (OR4)
0x02C (OR5)
0x034 (OR6)
0x03C (OR7)
EHTR
AM
Figure 14-4. Option Registers (OR n ) in UPM Mode
0
1
0
1
Table 14-7. OR n
The memory controller generates normal timing. No additional cycles are inserted.
1 idle clock cycle is inserted.
4 idle clock cycles are inserted.
8 idle clock cycles are inserted.
16 17 18
—
UPM Field Descriptions
XAM BCTLD
All zeros
Description
19
20
Meaning
—
22 23 24
BI
—
28
Access: Read/Write
TRLX EHTR EAD
29
Local Bus Controller
30
31
14-15