MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 1147

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

18.4.1.2
Whenever data must cross a bridge between two busses, the byte ordering of data on the source and
destination buses must be considered. The internal platform bus of this device is inherently big endian and
the PCI Express bus interface is inherently little endian.
There are two methods to handle ordering of data as it crosses a bridge—address invariance and data
invariance. Address invariance preserves the addressing of bytes within a scalar data element, but not the
relative significance of the bytes within that scalar. Conversely, data invariance preserves the relative
significance of bytes within a scalar, but not the addressing of the individual bytes that make up a scalar.
This device uses address invariance as its byte ordering policy.
As stated above, address invariance preserves the byte address of each byte on an I/O interface as it is
placed in memory or moved into a register. This policy can have the effect of reversing the significance
order of bytes (most significant to least significant and vice versa), but it has the benefit of preserving the
format of general data structures. Provided that software is aware of the endianness and format of the data
structure, it can correctly interpret the data on either side of the bridge.
Figure 18-125
address invariant bridge to a little endian destination.
Note that although the significance of the bytes within the scalar have changed, the address of the
individual bytes that make up the scalar have not changed. As long as software is aware that the source of
the data used a big endian format, the data can be interpreted correctly.
Freescale Semiconductor
PCI Express
Transaction
CplDLk
CplLk
Address lsbs
Significance
Byte lane
Supported as
Data
Byte Ordering
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
an Initiator
shows the transfer of a 4-byte scalar, 0x4142_4344, from a big endian source across an
No
No
Figure 18-125. Address Invariant Byte Ordering—4 bytes Outbound
Supported as
Table 18-117. PCI Express Transactions (continued)
MSB
000
41
a Target
0
Yes
source bus
No
Big endian
001
42
1
010
43
2
Completion for Locked Memory Read without Data. The only time that CplLk is
returned with UR status is when the controller receives a MRdLk command.
Completion for Locked Memory Read with Data
LSB
011
44
3
MSB
011
44
3
destination bus
Little endian
010
43
2
Definition
001
42
1
LSB
000
41
0
PCI Express Interface Controller
18-99