MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 1211

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
Nothing
System cycles
Cycles a read is returning data from
DRAM
Cycles a read or write transfers data
from (or to) DRAM
Pipelined read misses in the row open
table
Pipelined read or write misses in the
row open table
Non-pipelined read misses in the row
open table
Non-pipelined read or write misses in
the row open table
Pipelined read hits in the row open table
Pipelined read or write hits in the row
open table
Non-pipelined read hits in the row open
table
Non-pipelined read or write hits in the
row open table
Forced page closings not caused by a
refresh
Row open table misses
Row open table hits
Force page closings
Read-modify-write transactions due to
ECC
Forced page closings due to collision
with bank and sub-bank
Reads or writes from core
Event Counted
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 20-10. Performance Monitor Events
C:64 and Ref:20
DDR Memory Controller Events
Number
C1:121
C3:124
C5:120
C7:121
Ref:19
Ref:11
Ref:12
Ref:13
C2:64
C4:64
C6:64
C8:64
C1:64
C2:65
C3:64
C4:65
C5:64
Ref:0
General Events
Register counter holds current value
CCB (platform) clock cycles
Each data beat returned to the memory controller on the DRAM
interface
Each data beat transferred to or from the DRAM
Row open table read misses issued while a read is outstanding
Row open table read or write misses issued while a read or write
is outstanding
Row open table read misses issued when no reads are
outstanding
Row open table read or write misses issued when no reads or
writes are outstanding
Row open table read hits issued when a read is outstanding
Row open table read or write hits issued when a read or write is
outstanding
Row open table read hits issued when no reads are outstanding
Row open table read or write hits issued when no reads or
writes are outstanding
Precharges issued to the DRAM for any reason except refresh.
The possibilities are as follows:
Transactions that miss in the row open table
Transaction that hit in the row open table
Forced page closings including those due to refreshes
If ECC is enabled and a transaction requires byte enables, a
read-modify-write sequence is issued on the DRAM interface.
Increments if a new transaction must be issued to an active
bank and sub-bank that has a different row open
—
• A new transaction must be issued to an already active bank
• A new transaction must be issued, but the row open table is
• The BSTOPRE interval expired for an open row.
and sub-bank that has a different row open.
full and there is no bank/sub-bank match between the current
transaction and the row open table.
Description of Event Counted
Device Performance Monitor
20-17