MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 642

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller
Table 14-15
14.3.1.10
The LBC has the following registers for error management:
LTESR, shown in
however, write operations can clear but not set bits. A bit is cleared whenever the register is written and
the data in the corresponding bit location is a 1. For example, to clear only the write protect error bit
(LTESR[WP]) without affecting other LTESR bits, 0x0400_0000 should be written to the register. Note
that LTEATR[V] bit has to be cleared to register subsequent errors in LTESR.
14-24
8–31
Bits
0–7
Offset 0x0B0
Reset
•
•
•
•
•
W w1c
R BM
The transfer error status register (LTESR) indicates the cause of an error.
The transfer error check disable register (LTEDR) is used to enable (and disable) error checking.
The transfer error check interrupt register (LTEIR) enables reporting of errors through an interrupt.
The transfer error attributes register (LTEATR) captures source attributes of an error.
The transfer error address register (LTEAR) captures the address of a transaction that caused an
error.
Name
LSRT SDRAM refresh timer period. Determines, along with the timer prescaler (MRTPR), the timer period according
—
0
describes LSRT fields.
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
1
to the following equation:
Example: For a 266-MHz system clock and a required service rate of 15.6 µs, given PTP = 32, the LSRT
value should be 128 decimal. 128/(266 MHz/32) = 15.4 µs, which is less than the required service period of
15.6 µs.
Note that the reset value, 0x00, sets the maximum period to 256 × MRTPR[PTP] system clock cycles.
Reserved
Transfer Error Status Register (LTESR)
PAR
w1c
Figure
2
3
—
4
14-13, is a write-one-to-clear register. Reading LTESR occurs normally;
Figure 14-13. Transfer Error Status Register (LTESR)
w1c
WP
5
6
—
Table 14-15. LSRT Field Descriptions
7
ATMW ATMR
w1c
8
TimerPeriod
w1c
9
10 11
All zeros
—
Description
=
w1c
CS
12
--------------------------------------------- -
⎛
⎝
Fsystemclock
--------------------------------------- -
MRTPR PTP
13
LSRT
[
]
⎞
⎠
—
Freescale Semiconductor
Access: w1c
31