MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 128

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Memory Map
Windows must be a power-of-two size. To perform a translation or mapping function, the address of the
transaction is compared with the base address register of each window. The number of bits used in the
comparison is dictated by each window’s size attribute. When an address hits a window, if address
translation is being performed, the new translated address is created by concatenating the window offset
to the translation address. Again, the window’s size attribute dictates how many bits are translated.
2.2.1
The on-chip memory array of the MPC8533E can be configured as a memory-mapped SRAM ranging
from 64 Kbytes to 256 Kbytes. Configuration registers in the L2 cache controller set the base addresses
and sizes for these windows. When enabled, these windows supersede all other mappings of these
addresses for processor and global (snoopable) I/O transactions. Therefore, SRAM windows must never
overlap configuration space as defined by CCSRBAR. It is possible to have SRAM windows overlap local
access windows, but this is discouraged because processor and snoopable I/O transactions would map to
the SRAM while non-snooped I/O transactions would be mapped by the local access windows. Only if all
accesses to the SRAM address range are snoopable can results be consistent if the SRAM window overlaps
a local access window.
See
information about configuring SRAM windows.
2.2.2
CCSRBAR defines a window used to access all memory-mapped configuration, control, and status
registers. No address translation is done, so there are no associated translation address registers. The
window is always enabled with a fixed size of 1 Mbyte; no other attributes are attached, so there is no
associated size/attribute register. This window always takes precedence over all local access windows. See
Section 4.3.1.1.2, “Configuration, Control, and Status Base Address Register (CCSRBAR),”
Section 2.3, “Configuration, Control, and Status Register Map.”
2.2.3
As demonstrated in the address map overview in
Example,”
interface. This allows the internal interconnections of the MPC8533E to route a transaction from its source
to the proper target. No address translation is performed. The base address defines the high order address
bits that give the location of the window in the local address space. The window attributes enable the
window, define its size, and specify the target interface.
With the exception of configuration space (mapped by CCSRBAR), on-chip SRAM regions (mapped by
L2SRBAR registers), and default boot ROM, all addresses used by the system must be mapped by a local
access window. This includes addresses that are mapped by inbound ATMU windows; target mappings of
inbound ATMU windows and local access windows must be consistent.
The local access window registers exist as part of the local access block in the general utilities registers.
See
2-4
Section 7.3.1.3.1, “L2 Memory-Mapped SRAM Base Address Registers 0–1 (L2SRBARn),”
Section 2.3.4, “General Utilities Registers.”
local access windows associate a range of the local 36-bit address space with a particular target
SRAM Windows
Window into Configuration Space
Local Access Windows
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
A detailed description of the local access window
Section 2.1, “Local Memory Map Overview and
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and
for