MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 1314

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

F–G
Index-6
functional description, 15-126
gigabit Ethernet channel operation, 15-141
hash function
initialization/application information, 15-180–15-206
interrupts, 15-152–15-155
lossless flow control, 15-170
MAC functionality, 15-64–15-79
memory map/register definition, 15-12
modes of operation, 15-4
overview, 1-18, 15-1
physical interface connections, 15-126
quality of service (QoS) support, 15-162–15-170
flow control, 15-151
frame reception, 15-144
frame recognition, 15-147
frame transmission, 15-143
initialization sequence, 15-141
internal and external loop back, 15-155
inter-packet gap time, 15-155
Magic Packet mode, 15-151
preamble customization, 15-145
RMON support, 15-147
algorithm, 15-149
registers, 15-107–15-108
gigabit Ethernet channel, 15-141
see also eTSEC, configuration
interrupt coalescing, 15-153
interrupt registers, 15-24–15-29
back pressure determination and free buffers, 15-170
software use of hardware-initiated back pressure, 15-172
configuration, 15-64
CSMA/CD control, 15-64
handling packet collisions, 15-64
packet flow control, 15-65
PHY links control, 15-66
registers, 15-66–15-79
detailed memory map, 15-13–15-22
eTSEC2–4 controller offsets, 15-22, B-40
top-level module map, 15-13
RMON support, 15-79
gigabit media-independent interface (GMII), 15-128
media-independent interface (MII), 15-127
reduced gigabit media-independent interface (RGMII),
reduced media-independent interface (RMII), 15-127
reduced ten-bit interface (RTBI), 15-132
ten-bit interface (TBI), 15-131
receive queue filer, 15-162
soft reset and reconfiguring procedure, 15-142
soft reset and reconfiguring procedure, 15-142
by frame count threshold, 15-153
by timer threshold, 15-154
15-129
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
eTSEC2 signals as GP I/O, see Global utilities,
External system configuration
External writes, see L2 cache/SRAM, stashing
F
Full-on mode (power), 1-20
G
General-purpose I/O (PCI and eTSEC2)
Global utilities
register descriptions, 15-22–15-126
signals, 15-6–15-12
TCP/IP off-load, 15-157–15-162
POR (LAD[0:31]) status, 4-21, 19-11
see Global utilities
clock out
DDR calibration status, 19-21
DDR controller
DMA signal multiplex control register (PMUXCR), 19-13,
features, 19-1
functional description, 19-25
general-purpose I/O signals (PCI and eTSEC2)
transmission scheduling, 15-168
by acronym, see Register Index
DMA attribute registers, 15-110–15-112
FIFO registers, 15-109–15-110
general control and status registers, 15-22–15-36
hash function registers, 15-107–15-108
lossless flow control registers, 15-112–15-114
MAC registers, 15-66–15-79
MIB registers, 15-79–15-107
receive control and status registers, 15-48–15-63
ten-bit interface registers, 15-115–15-126
transmit control and status registers, 15-36–15-48
FIFO interface signal summary, 15-140
see also Signals, eTSEC
summary, 15-6
frame control blocks, 15-158
receive path off-load, 15-160
transmit path off-load, 15-158
general-purpose I/O signals
CLK_OUT signal, 19-3, 19-23
clock out control register (CLKOCR), 19-23
overview, 19-1
clock disable, 19-22
control register (GPIOCR), 19-11
GPOUT[24:31] signals, 19-3
input data register (GPINDR), 19-13
operation of, 19-33
output data register (GPOUTDR), 19-12
19-33
Freescale Semiconductor
Index