MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 495

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

The header dword specifies the security operation to be performed, the execution unit(s) needed, and the
modes for each execution unit. The pointer dwords, all of which have the same format, contain pointer and
length information for locating input or output data parcels (such as keys, context, or text-data). The large
number of pointers provided in the descriptor allows for multi-algorithm operations that require fetching
of multiple keys, as well as fetch and return of contexts. Any pointer dword that is not needed can be given
a length of zero, and the channel will skip over the corresponding operations.
SEC descriptors include scatter/gather capability, which means that each pointer in a descriptor can be
either a direct pointer to a contiguous parcel of data, or can be a pointer to a link table which is a list of
pointers and lengths used to assemble the data parcel. When a link table is used to read input data, this is
referred to as a gather operation; when used to write output data, it is referred to as a scatter operation.
12.3.2
Descriptors are created by the host to guide the SEC through required cryptographic operations. The
header dword defines the operations to be performed, the mode for each operation, and internal addressing
used by the controller and channel for internal data movement. The fields that must be supplied to SEC are
shown in the field rows of
to create proper headers for each cryptographic operation.
Header dword bit definitions are described below.
Freescale Semiconductor
12–15
16–23
24–28 DESC_TYPE Descriptor type. This field, along with DIR, determines the sequence of actions to be performed by the
Field
4–11
Bits
0–3
29
0
EU_SEL0
EU_SEL0
EU_SEL1
MODE0
MODE1
Name
—
Descriptor Format: Header Dword
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
3
4
Primary EU select. See
possible values.
Primary mode. Mode data used to program the primary EU. The mode data is to the chosen EU. This
field is passed directly to bits 56–63 of the mode register in the selected EU.
Secondary EU select. See
possible values.
Secondary mode. Mode data used to program the primary EU. The mode data is to the chosen EU. This
field is passed directly to bits 56–63 of the mode register in the selected EU.
channel and selected EUs using the blocks of data listed in the rest of the descriptor. The attributes
determined include the direction of data flow for each data block, which EU (primary or secondary) is
accessed, what snooping options are used, and which internal EU addresses are accessed.
See
Reserved.
OP_0
Section 12.3.2.2, “Selecting Descriptor Type—DESC_TYPE,”
MODE0
Figure
Table 12-4. Header Dword Bit Definitions
12-4, and described in
11
Figure 12-4. Header Dword
Section 12.3.2.1, “Selecting Execution Units—EU_SEL0 and EU_SEL1,”
12
Section 12.3.2.1, “Selecting Execution Units—EU_SEL0 and EU_SEL1,”
EU_SEL1
15
OP_0
OP_1
OP_1
16
Table
Description
MODE1
12-4. The SEC device drivers allow the host
23
for possible values.
24
DESC_TYPE
Security Engine (SEC) 2.1
28
—
29
DIR
30
for
12-17
DN
31
for