MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 335

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

9.4.1.3
DDR SDRAM timing configuration register 3, shown in
time, which is combined with TIMING_CFG_1[REFREC] to determine the full refresh recovery time.
Freescale Semiconductor
18–20
21–23
24–28
29–31
Bits
Offset 0x100
Reset
W
R
ROW_BITS_CS_ n Number of row bits for SDRAM on chip select n . See
COL_BITS_CS_ n
0
DDR SDRAM Timing Configuration 3 (TIMING_CFG_3)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Name
—
—
Figure 9-4. DDR SDRAM Timing Configuration 3 (TIMING_CFG_3)
Table 9-7. CS n _CONFIG Field Descriptions (continued)
Reserved
details.
000 12 row bits
001 13 row bits
010 14 row bits
011 15 row bits
100 16 row bits
101–111 Reserved
Reserved
Number of column bits for SDRAM on chip select n. For DDR, the decoding is as follows:
000 8 column bits
001 9 column bits
010 10 column bits
011 11 column bits
100–111 Reserved
—
12 13
EXT_REFREC
All zeros
Figure
15 16
Description
9-4, sets the extended refresh recovery
Table 9-42Table
—
9-41and
Access: Read/Write
DDR Memory Controller
Table 9-42
31
for
9-13