MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 343

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Table 9-12
Freescale Semiconductor
Bits
5–7
8–9
10
11
12
13
0
1
2
3
4
SDRAM_TYPE
DYN_PWR
MEM_EN
ECC_EN
RD_EN
describes the DDR_SDRAM_CFG fields.
32_BE
SREN
Name
8_BE
—
—
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0 SDRAM interface logic is disabled.
1 SDRAM interface logic is enabled. Must not be set until all other memory configuration
0 SDRAM self refresh is disabled during sleep. Whenever self-refresh is disabled, the system is
1 SDRAM self refresh is enabled during sleep.
causes the core to generate a machine check interrupt unless it is disabled (by clearing
HID1[RFXE]). If RFXE is zero and this error occurs, ERR_DISABLE[MBED] and
ERR_INT_EN[MBEE] must be zero and ECC_EN must be one to ensure an interrupt is generated.
See
0 No ECC errors are reported. No ECC interrupts are generated.
1 ECC is enabled.
0 Indicates unbuffered DIMMs.
1 Indicates registered DIMMs.
Note that RD_EN and 2T_EN must not both be set at the same time.
Reserved
initialization sequence to DRAM via Mode Register Set and Extended Mode Register Set
commands. Default value is 010 designating DDR1 SDRAM.
000–001Reserved
010 DDR1 SDRAM
011 DDR2 SDRAM
100 Reserved
101 Reserved
110 Reserved
111 Reserved
Reserved
0 Dynamic power management mode is disabled.
1 Dynamic power management mode is enabled. If there is no ongoing memory activity, the
Reserved
0 64-bit bus is used.
1 32-bit bus is used.
0 4-beat bursts are used on the DRAM interface.
1 8-beat bursts are used on the DRAM interface.
Note: 8-beat bursts may be used by DDR1 (SDRAM_TYPE = 010), and only when using 32-bit bus
DDR SDRAM interface logic enable.
Self refresh enable (during sleep).
ECC enable. Note that uncorrectable read errors may cause the assertion of core_fault_in , which
Registered DIMM enable. Specifies the type of DIMM used in the system.
Type of SDRAM device to be used. This field will be used when issuing the automatic hardware
Dynamic power management mode
32-bit bus enable.
8-beat burst enable.
parameters have been appropriately configured by initialization code.
responsible for preserving the integrity of SDRAM during sleep.
SDRAM CKE signal is negated.
Section 6.10.2, “Hardware Implementation-Dependent Register 1 (HID1).”
Table 9-12. DDR_SDRAM_CFG Field Descriptions
mode (32_BE = 1); DDR2 (SDRAM_TYPE = 011) must use 4-beat bursts, even when using
32-bit bus mode
Description
DDR Memory Controller
9-21