MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 551

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

12.4.6.7
The AESU interrupt control register, shown in
given error (as defined in
corresponding bit in this register is set, then the error is ignored; no error interrupt occurs and the interrupt
status register is not updated to reflect the error. If the corresponding bit is not set, then upon detection of
an error, the interrupt status register is updated to reflect the error, causing assertion of the error interrupt
signal, and causing the module to halt processing.
Table 12-43
Freescale Semiconductor
Address AESU 0x3_4038
0–48
Bits Name
Bits Name
58
59
60
61
62
63
49
50
Reset
W
R
OFE
OFU Output FIFO underflow. The AESU Output FIFO was read while empty.
IFO
IFE
ICE
—
—
—
—
0
Output FIFO error. The AESU output FIFO was detected non-empty upon write of AESU data size register.
0 No error detected
1 Output FIFO non-empty error
Input FIFO error. The AESU input FIFO was detected non-empty upon generation of done interrupt.
0 No error detected
1 Input FIFO non-empty error
Reserved
Input FIFO overflow. The AESU Input FIFO was pushed while full.
0 No error detected
1 Input FIFO has overflowed
Note: When operated through channel-controlled access, the SEC implements flow control, and FIFO size is not
0 No error detected
1 Output FIFO has underflow error
Reserved
describes the AESU interrupt control register fields.
Reserved
Integrity check error. The supplied ICV did not match the one computed by the AESU.
0 Integrity check error enabled
1 Integrity check error disabled
Reserved
AESU Interrupt Control Register (AESUICR)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 12-42. AESU Interrupt Status Register Field Descriptions (continued)
a limit to data input. When operated through host-controlled access, the AESU cannot accept FIFO inputs
larger than 256 bytes without overflowing.
—
Table 12-43. AESU Interrupt Control Register Field Descriptions
Section 12.4.6.6, “AESU Interrupt Status Register
Figure 12-53. AESU Interrupt Control Register
48
ICE
49
—
50
51
IE
Figure
ERE CE KSE DSE ME
52
Description
Description
53
12-53, controls the result of detected errors. For a
1000
54
55
56
AE OFE IFE
57
(AESUISR)”), if the
58
59
Security Engine (SEC) 2.1
—
60
Access: Read/write
IFO OFU —
61
62
12-73
63