MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 797

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Table 15-39
Freescale Semiconductor
16–22
24–25
1–11
\
Bits
12
13
14
15
23
26
27
28
29
0
Sync’d Rx EN Receive enable synchronized to the receive stream. (Read-only)
Reset Rx Fun Reset receive function block. This bit is cleared by default.
Reset Rx MC Reset receive MAC control block. This bit is cleared by default.
Reset Tx Fun Reset transmit function block. This bit is cleared by default.
Reset Tx MC Reset transmit MAC control block. This bit is cleared by default.
Soft_Reset
Loop Back
Rx_Flow
Tx_Flow
Rx_EN
Name
describes the fields of the MACCFG1 register.
—
—
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Soft reset. This bit is cleared by default. See
Procedure,”
0 Normal operation.
1 Place the entire MAC in reset except for the host interface.
Reserved
0 Normal operation.
1 Place the receive part of the MAC in reset. This block detects control frames and contains the pause
0 Normal operation.
1 Place the transmit part of the MAC in reset. This block multiplexes data and control frame transfers.
0 Normal operation.
1 Place the receive function in reset. This block performs the receive frame protocol.
0 Normal operation.
1 Place the transmit function in reset. This block performs the frame transmission protocol.
Reserved
Loop back. This bit is cleared by default.
0 Normal operation.
1 Loop back the MAC transmit outputs to the MAC receive inputs.
Reserved
Receive flow. This bit is cleared by default.
0 The receive MAC control ignores PAUSE flow control frames.
1 The receive MAC control detects and acts on PAUSE flow control frames.
Transmit flow. This bit is cleared by default.
0 The transmit MAC control may not send PAUSE flow control frames if requested by the system.
1 The transmit MAC control may send PAUSE flow control frames if requested by the system.
0 Frame reception is not enabled.
1 Frame reception is enabled.
Receive enable. This bit is cleared by default. If set, prior to clearing this bit, set DMACTRL[GRS] then
confirm subsequent occurrence of the graceful receive stop interrupt (IEVENT[GRSC] is set).
0 The MAC may not receive frames from the PHY.
1 The MAC may receive frames from the PHY.
timers.
It also responds to XOFF PAUSE control frames.
for more information on setting this bit.
Table 15-39. MACCFG1 Field Descriptions
Description
Section 15.6.3.2, “Soft Reset and Reconfiguring
Enhanced Three-Speed Ethernet Controllers
15-67