MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 1008

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MPC8533EVTALFA

Manufacturer Part Number
MPC8533EVTALFA
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTALFA

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
783-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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Part Number:
MPC8533EVTALFA
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Quantity:
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PCI Bus Interface
17.3.2
The PCI Local Bus Specification defines the configuration registers contained within the PCI
configuration header from 0x00 through 0x3F.
implemented by the device.
Table 17-49
configuration header registers. Detailed descriptions of these registers are provided in the PCI Local Bus
Specification.
17.3.2.1
The PCI vendor ID register, shown in
17-30
Offset 0x00
Reset
Reserved
Bus Base Class Code
W
R
PCI Bus MAX_LAT
BIST Control
15
0
PCI Configuration Header
in
PCI Vendor ID Register—Offset 0
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PCI Bus Arbiter Configuration
Section 17.4.2.11.1, “PCI Configuration Space Header,”
0
PCI Configuration and Status Register Base Address Register (PCSRBAR)
PCI Bus Status
Subsystem ID
0
Device ID
Figure 17-24. Common PCI Configuration Header
1
PCI Bus MIN_GNT
Subclass Code
64-Bit High Memory Base Address Register
64-Bit High Memory Base Address Register
64-Bit Low Memory Base Address Register
64-Bit Low Memory Base Address Register
Header Type
1
Figure 17-25. PCI Vendor ID Register
32-Bit Memory Base Address Register
Figure
0
17-25, is used to identify the manufacturer of the part.
Figure 17-24
0
Bus Programming Interface
Vendor ID
1
PCI Bus Interrupt Pin
Bus Latency Timer
x
00
0
lists the common PCI configuration header as
1
Subsystem Vendor ID
PCI Bus Command
PCI Bus Function
0
Vendor ID
provides a summary of the PCI
PCI Bus Capability Pointer 34
1
PCI Bus Interrupt Line
Bus Cache Line Size
Revision ID
0
Freescale Semiconductor
Access: Read only
1
Offset (Hex)
Address
1
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
38
3C
40
44
1
0

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