MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 1319

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Index
LOE (LBC GPCM output enable) signal, 14-6
Freescale Semiconductor
signals summary, 14-4
UPM interfaces, 14-58–14-78
voltage selection, 19-20
ZBT SRAM interface, 14-96
configurations supported, 14-47
device-specific parameters, 14-51
limitations, 14-87–14-95
maximum SDRAM supported, 14-86
page hit checking, 14-50
page management, 14-50
parity support, 14-95
power-on initialization, 14-48
refresh, 14-57
SDRAM mode
timing, 14-55
transactions, 14-57
see also Signals, LBC
block diagram, 14-59
example interface, 14-73
extended hold time (reads), 14-73
programming the UPMs, 14-62
RAM array, 14-64
signal timing, 14-64
synchronous UPWAIT (early transfer acknowledge),
UPM mode
UPM requests, 14-59
registers, 14-16, 14-21
activate-to-read/write interval, 14-52
CAS latency, 14-53
external buffers, 14-54
MODE-SET commands, 14-57
precharge-to-activate interval, 14-52
refresh recovery, 14-54
refresh timing, 14-58
write recovery, 14-53
address multiplexing, 14-70
byte select signal timing, 14-68
chip select signal timing, 14-67
data timing, 14-71
general purpose signal timing, 14-69
LGPL[0:5] timing (LAST), 14-71
loop control, 14-69
RAM word definition, 14-65
REDO, 14-69
wait mechanism (WAEN), 14-71
registers, 14-15, 14-17
exception requests, 14-62
memory access requests, 14-60
refresh timer requests, 14-61
software requests, 14-61
14-72
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
LPBSE (LBC parity byte select) signal, 14-6
LR (link register), see e500 core, registers
LSDA10 (LBC SDRAM A10) signal, 14-6
LSDCAS (LBC SDRAM CAS) signal, 14-6
LSDDQM[0:3] (LBC SDRAM data mask) signal, 14-6
LSDRAS (LBC SDRAM RAS) signal, 14-6
LSDWE (LBC SDRAM write enable) signal, 14-6
LSYNC_IN (LBC PLL synchronization in) signal, 14-8
LSYNC_OUT (LBC PLL synchronization out) signal, 14-8
LWE[0:3] (LBC GPCM write enable) signals, 14-6
M
MA[0:14] (DDR address bus) signals, 9-7
MAC functionality, see eTSEC, MAC functionality
Machine check
MAS0–MAS6 (MMU assist registers 0–6), see e500 core,
MBA[0:1] (DDR logical bank address) signals, 9-7
MCAR (machine check address register), see e500 core,
MCAS (DDR column address strobe) signal, 9-7
MCK[0:5] (DDR clock output complement) signals, 9-9
MCK[0:5] (DDR clock output) signals, 9-9
MCKE[0:3] (DDR clock enable) signals, 9-9
MCP (processor machine check) signal, 10-8
MCS[0:3] (DDR chip select) signals, 9-8
MCSR (machine check syndrome register), see e500 core,
MCSRR0–1 (machine check save/restore registers 0–1), see
MDIC[0:1] (DDR driver impedance calibration) signals, 9-8
MDM[0:8] (DDR SDRAM data output mask) signals, 9-8
MDQ[0:8] (DDR data bus strobe) signals, 9-6, 9-42
MDVAL (DDR/LBC debug mode data valid) signal, 4-20,
MECC[0:5] (DDR error correcting code) signals as debug,
MECC[0:7] (DDR error correcting code) signals, 4-20, 9-6
Memory maps
MCP (processor machine check) signal, 10-8
mcp summary register (MCPSUMR), 19-17
SRESET (soft reset) signal, 4-8
CCSR memory, 2-4
registers
registers
registers
e500 core, registers
14-8, 21-3, 21-6
21-3, 21-7
accessing CCSR memory from external masters, 2-10,
CCSR map, complete list of memory-mapped registers
CCSR organization, 2-11
CCSR registers, 2-10–2-14
device-specific utilities, 2-13
general utilities registers, 2-12
programmable interrupt controller (PIC) space, 2-13
2-11
(by offset), 2-14
Index-11
M–M