MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 450

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Programmable Interrupt Controller
10.5.1.1
Most PIC control and status registers are readable and return the last value written. The exceptions to this
rule are as follows:
The following guidelines are recommended when the PIC unit is programmed in mixed mode
(GCR[M] = 1):
In addition, the following initialization sequence is recommended:
Depending on the interrupt system configuration, the PIC may generate spurious interrupts to clear
interrupts latched during power-up. A spurious or non-spurious vector is returned for an interrupt
acknowledge cycle in this case. See the programming note below for the non-spurious case.
10-54
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1. Write the vector, priority, and polarity values in each interrupt’s vector/priority register, leaving
2. Clear the CTPR (CTPR = 0x0000_0000).
3. Program the PIC to mixed mode by setting GCR[M].
4. Clear the MSK bit in the vector/priority registers to be used.
5. Perform a software loop to clear all pending interrupts:
6. Set the processor CTPR value to the desired value.
7. Set MER as desired (for example, 0x0000_000F enables all message interrupts). See
IPI dispatch registers and the EOI register, which return zeros on reads.
Activity bit (A) of the vector/priority registers, which returns the value according to the status of
the current interrupt source.
IACK register, which returns the vector of highest priority which is currently pending, or the
spurious vector.
Reserved fields always return 0.
All PIC registers must be located in a cache-inhibited and guarded area (through the processor
MMU).
The PIC portion of the address map must be set-up appropriately.
their MSK (mask) bit set. This is required only if interrupts are used.
— Load counter with FPR[NIRQ].
— While counter > 0, perform IACK and EOIs to guarantee all the interrupt pending and
Section 10.3.5.2, “Message Enable Register
in-service registers are cleared.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PIC Registers
Because the default polarity/sense for external interrupts is edge-sensitive,
and edge-sensitive interrupts are not cleared until they are acknowledged, it
is possible for the PIC to store spurious edges detected during power-up as
pending external interrupts. If software permanently configures an external
interrupt source to be edge-sensitive, it may receive the vector for the
interrupt source and not a spurious interrupt vector when software clears the
mask bit. This can occur once for any edge-sensitive interrupt when its mask
bit is first cleared and the PIC is in mixed mode.
NOTE:
(MER),” for more information.
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