MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 558

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
12.4.7.1
The KEU mode register, shown in
The mode register is cleared when the KEU is reset or re-initialized. Setting a reserved mode bit generates
a data error. Setting both the GSM and EDGE bits to one generates a data error. If the KEU mode register
is modified during processing, a context error is generated.
Table 12-44
12-80
Address KEU 0x3_E000
0–55
Bits
56
57
58
Reset
W
R
EDGE Select EDGE A5/3 blocks
Name
GSM
CICV Compare integrity check values.
0
—
describes the KEU mode register fields.
KEU Mode Register (KEUMR)
Reserved
Select GSM A5/3 blocks
0 GSM A5/3 blocks not selected
1 GSM A5/3 blocks selected
Note 1: For GSM A5/3, Two 114-bit blocks are required to be produced each 4.615mS slot. If GSM = 1, the first
Note 2: If GSM = 0, 228 contiguous bits may be read with successive reads of the output FIFO. In this case the
Note 3: If GSM is set to 1, while EDGE = 1, an interrupt/error will be generated.
0 Normal operation; no ICV comparison.
1 After the ICV is computed, compare it to the data in the KEU’s ICV_In register. If the ICVs do not match, send
0 EDGE A5/3 blocks not selected
1 EDGE A5/3 blocks selected
Note 1: For EDGE A5/3, Two 348-bit blocks are required to be produced each 4.615mS slot. If EDGE = 1, the
Note 2: If EDGE = 0, 696 contiguous bits may be read with successive reads of the output FIFO. In this case
Note 3: If EDGE is set to 1, whilst GSM = 1, an interrupt/error will be generated.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
an error interrupt to the channel. Only applicable to
read of the output FIFO retrieves the first 64 bits of block 1. The second read of the output FIFO retrieves
the next 50 bits of block 1 (the remaining bits of this 64-bit word are set to zero). The third read of the output
FIFO retrieves the first 64 bits of block 2, while a fourth read of the output FIFO retrieves the next 50 bits of
block 2 (the remaining bits of this 64-bit word are set to zero).
host (application) will be responsible for handling the A5/3 block formatting.
first five reads of the output FIFO retrieve the first 320 bits of block 1. The sixth read of the output FIFO
retrieves the final 28 bits of block 1 (the remaining bits of the sixth 64-bit word are set to zero). The next five
reads of the output FIFO retrieve the first 320 bits of block 2. The following read of the output FIFO retrieves
the final 28 bits of block 2 (the remaining bits of this 64-bit word are set to zero).
the host (application) will be responsible for handling the A5/3 block formatting.
Table 12-44. KEU Mode Register Field Descriptions
—
Figure
Figure 12-57. KEU Mode Register
12-57, contains several bits which are used to program the KEU.
55
All zeros
Description
GSM CICV EDGE
56
57
58
PE
59
INT
60
Freescale Semiconductor
—
Access: Read/write
61
62
ALG
63