MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 900

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
The algorithm checks registers TQUEUE[EN0–EN7] for
ring_empty(),
throughput for that ring is:
15.6.6
The eTSEC DMA subsystem is designed to be able to support simultaneous receive and transmit traffic at
gigabit line rates. If the host memory has sufficient bandwidth to support such line rates, then the principle
cause of overflow on receive traffic will be due to a lack of Rx BDs. Thus, the long term receive throughput
will be determined by the rate at which software can process receive traffic. If a user desires to prevent
dropped packets, they can inform the far-end link to stop transmission while the software processing
catches up with the backlog. The current hardware initiated back-pressure mechanism (the RX_PAUSE
register) is designed to allow for momentary backlogging of the Rx DMA (due to host memory
contention), not a lack of Rx BDs.
To avoid overflow in the latter case, back pressure must be applied to the far-end transmitter before the Rx
descriptor controller encounters a non-empty BD and halts with a BSY error. As there is lag between
application of back-pressure and response of the far-end, the pause request must be issued while there are
still BDs free in the ring. In the traditional eTSEC descriptor ring programming model, there is no way for
hardware to know how many free BDs are available, so software must initiate any pause requests required
during operation. If software is backlogged, the request may be not be issued in time to prevent BSY errors.
To allow the eTSEC to generate the pause request automatically, additional information (a pointer the last
free BD and ring length) is required.
15.6.6.1
Ultimately, the rate of data reception is determined by how quickly software can release buffers back into
the receive ring(s). Each time a buffer is freed, the associated BD has its empty bit set and hardware is free
to consume both. Thus the number of free BDs in a given Rx ring indicates how close hardware is to the
end of that ring. To prevent data loss, back pressure should be applied when the number of free BDs drops
below some critical level. The number of BDs that can be consumed by an incoming packet stream while
back-pressure takes effect is determined by several factors, such as: receive traffic profile, transmit traffic
profile, Rx buffer size, physical transmission time between eTSEC and far-end device and intra-device
latency. Theoretically, the worst case will be:
15-170
rate of queue[k] (K = 1 to 7) = (available bandwidth) * WTk/(sum(WTi) + 6WT0)
rate of queue(0) = (available bandwidth) * 7 * WT0/(sum(WTi) + 6WT0)
where i = 0 to 7
Lossless Flow Control
Back Pressure Determination via Free Buffers
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
and TRxWT for
FreeBDsRequired
weight()
=
------------------------------------------------------- -
MinFrameSize
. For TxBD ring k, having a weight WTk, the long term average
MaxFrameSize
+
IFG
enabled()
+
MaxFrameSize
--------------------------------------- -
RxBufferSize
, TSTAT[THLT0–THLT7] for
+
LinkDelay
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