MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 171

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

4.4.3.3
The SEC mode configuration input, shown in
Complex Bus (CCB) Clock to the SEC Clock. In the default 3:1 (CCB CLK: SEC CLK) setting, the SEC
is clocked at one-third the frequency of the e500 Core Complex Bus (CCB) Clock. The ratio may be
changed to 2:1 if the CCB Clock is below the threshold stated in the MPC8533E Integrated Processor
Hardware Specifications.
Note that the value latched on this signal during POR is accessible through the memory-mapped
PORDEVSR2 described in
4.4.3.4
The MPC8533E defines the default boot ROM address range to be 8 Mbytes at address 0x0_FF80_0000
to 0x0_FFFF_FFFF. However, which peripheral interface handles these boot ROM accesses can be
selected at power on.
The boot ROM location inputs, shown in
to the boot vector and the default boot ROM region of the local address map are directed to the interface
specified by these inputs.
Note that the values latched on these signals during POR are accessible through the memory-mapped
PORBMSR (POR boot mode status register) described in
Register (PORBMSR).”
Freescale Semiconductor
Functional
Default (1)
LWE_B[0]
Signal
Functional Signals
TSEC1_TXD[6:4]
Default (111)
Reset Configuration
SEC Frequency Ratio Configuration
Boot ROM Location
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
cfg_sec_freq
Name
Reset Configuration Name
cfg_rom_loc[0:2]
Section 19.4.1.4, “POR Device Status Register
(Binary)
Value
0
1
Table 4-11. SEC Mode Configuration
Table 4-12. Boot ROM Location
Enables the SEC in 2:1 (CCB CLK: SEC CLK) mode with respect to e500 Core
Complex Bus (CCB) Clock
Enables the SEC in 3:1 (CCB CLK: SEC CLK) mode with respect to e500 Core
Complex Bus (CCB) Clock (default).
Table
Table
4-12, select the physical location of boot ROM. Accesses
(Binary)
Value
000
001
010
011
100
101
110
111
4-11, is used to establish the ratio of the e500 Core
PCI
DDR SDRAM
PCI Express 2
PCI Express 3
PCI Express 1
Local bus GPCM—8-bit ROM
Local bus GPCM—16-bit ROM
Local Bus GPCM—32-bit ROM (default)
Section 19.4.1.2, “POR Boot Mode Status
Meaning
(PORDEVSR).
Meaning
Reset, Clocking, and Initialization
4-13