MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 1248

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Debug Features and Watchpoint Facility
Table 21-25
21.4
The debug features on the MPC8533E use the LBC interfaces, and the DDR SDRAM interface.
21.4.1
Debug information that is common to all the interfaces is the source ID (SID). The transaction source ID
provides enough information to determine which block or port originated a transaction including the
distinction between instruction and data fetches from the processor core.
interpretation for the 5-bit SID field. Note that the table also includes ports that are only slaves, such as
local memory. These ports are always targets. As such, the value shown represents a target ID (TID) and
not a source ID. For ports that can function in both capacities, the value indicates source ID when
mastering transactions, and target ID when responding as slave. The TID field is only meaningful when
one of the following participates in the transaction:
21-24
8–31
Bits
0–4
5–7
•
•
•
The e500 coherency module (ECM) dispatch bus
The watchpoint monitor (WMCR1[IFSEL] = 000)
The trace buffer (TBCR1[IFSEL] = 000)
Name
SEL
Functional Description
—
—
Source and Target ID
describes the TOSR fields.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
Select. Selects the source for TRIG_OUT
000 READY signal. Multiplexed with TRIG_OUT. Basic device state indicator. READY asserts whenever the
001 Selects the watchpoint monitor hit indication
010 Selects the trace buffer hit indication
011 Selects the performance monitor overflow indication
Reserved
device is not in reset or not asleep. See
about the reset sequence, and
management states.
Table 21-25. TOSR Field Descriptions
Chapter 19, “Global Utilities,”
Chapter 4, “Reset, Clocking, and Initialization,”
Description
for more information about power
Table 21-26
shows the values and
Freescale Semiconductor
for more details