MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 763

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MPC8533EVTALFA

Manufacturer Part Number
MPC8533EVTALFA
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTALFA

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
783-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

Available stocks

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Part Number
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Quantity
Price
Part Number:
MPC8533EVTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
The different interface configurations indicated by registers ECNTRL and MACCFG2 are summarized in
Table
15.5.3.1.7
PTV is a 32-bit register written by the user to store the pause duration used when the eTSEC initiates an
IEEE 802.3 PAUSE control frame via TCTRL[TFC_PAUSE]. The low-order 16 bits (PT) represent the
pause time and the high-order 16 bits (PTE) represent the extended pause control parameter. The pause
time is measured in units of pause_quanta, equal to 512 bit times. The pause time can range from 0 to
65,535 pause_quanta, or 0 to 33,553,920 bit times. See
details.
Freescale Semiconductor
30–31
Bits
Offset eTSEC1:0x2_4028; eTSEC3:0x2_6028
Reset
29
15-11.
W
R
Figure 15-8
0
FIFO 8-bits
TBI 1 Gbps
RTBI 1 Gbps
GMII 1 Gbps
RGMII 1 Gbps
RGMII 100 Mbps
RGMII 10 Mbps
MII 10/100 Mbps
RMII 100 Mbps
RMII 10 Mbps
Name
RMM
Interface Mode
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Pause Time Value Register (PTV)
Reduced-pin mode for 10/100 interfaces. If this bit is set, a RMII pin interface is expected. Valid only if
FIFM = 0 and TBIM = 0. RPM and RMM are never set together. This register can be pin-configured at
reset to 0 or 1. See
0 MII, RGMII, GMII, TBI, or RTBI mode configuration
1 RMII mode
Reserved
describes the definition for the PTV register.
Table 15-10. ECNTRL Field Descriptions (continued)
Table 15-11. eTSEC Interface Configurations
FIFM
PTE
1
0
0
0
0
0
0
0
0
0
Figure 15-8. PTV Register Definition
Section 4.4.3, “Power-On Reset Configuration.”
GMIIM
0
0
0
1
1
1
1
0
0
0
TBIM
ECNTRL Field
0
1
1
0
0
0
0
0
0
0
All zeros
15 16
RPM
Section 15.6.3.9, “Flow Control,”
Description
1
0
1
0
1
1
1
0
0
0
R100M
1
0
1
0
Enhanced Three-Speed Ethernet Controllers
RMM
0
0
0
0
0
0
1
1
MACCFG2 Field
PT
I/F Mode
10
10
10
10
01
01
01
01
01
Access: Read/Write
for additional
15-33
31

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