MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 581

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

12.5.2
The channel can assert both DONE and ERROR interrupts to the controller. When the interrupt generation
conditions have been met, the channel asserts the appropriate interrupt. The status of the registered channel
interrupts is available in the controller interrupt status register. The channel does not have an internal
interrupt controller, but the SEC controller can be programmed to block channel interrupts via its interrupt
mask register (see
12.5.2.1
Whether and when a channel DONE interrupt is generated depends on the setting of the channel
configuration register NT and CDIE bits in the CCR (see
done interrupt enable) is set, the channel will generate an interrupt event after every successfully
completed descriptor (notification type set to global), or after each successfully completed descriptor with
the DN (done notification) bit set in the header word of the descriptor.
Even if multiple channel done interrupt events are generated by a channel before the first can be cleared
by the host, the interrupt events are not lost. The controller queues channel done interrupts from each
channel (see
12.5.2.2
The channel error interrupt is generated when an error condition occurs during descriptor processing. The
channel error interrupt will be asserted as soon as the error condition is detected. The type of error
condition is reflected the ERROR field of the channel pointer status register (CPSR). Refer to
for a complete listing of error types.
12.5.2.3
Channel reset is asserted when the host sets the RESET bit in the channel configuration register (CCR).
The effect of software reset on the channel varies according to what the channel is doing when the bit is set:
Freescale Semiconductor
LTB0
LTB1
LTB2
LTB3
•
•
If the RESET bit is set while the channel is requesting an EU assignment from the controller, the
channel cancels its request by asserting the release output signals. The channel then resets all the
registers, clears the RESET bit and returns the control state machine to the idle state.
If the RESET bit is set after the channel has been dynamically assigned an EU, the channel requests
a write from the controller to set the software reset bit of the EU. A write to reset the secondary
0
Channel Interrupts
Section 12.6.4, “Controller
Channel Done Interrupt
Channel Error Interrupt
Channel Reset
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
SEGLEN
SEGLEN
SEGLEN
SEGLEN
Section 12.6.5.2, “Interrupt Mask Register
15 16
—
—
—
—
Figure 12-78. Link Table Buffer
21 22 23 24 27 28 31 32
R N
R N
R N
R N
Interrupts”).
—
—
—
—
EPTR
EPTR
EPTR
EPTR
Figure
(IMR)”).
12-72). Assuming the CDIE (channel
SEGPTR
SEGPTR
SEGPTR
SEGPTR
Security Engine (SEC) 2.1
Table 12-55
12-103
63