MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 1188

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Global Utilities
19.5.1.5.1
In doze mode, the e500 core suspends instruction execution, significantly reducing the power consumption
of the core. Snooping of the L1 data cache is still supported and thus the data in the data cache is kept
coherent. Interrupts directed to the core as described in
are monitored by the device and cause the MPC8533E to use the defined handshake mechanism to exit the
core from doze mode to allow the core to recognize and process the interrupt; however, unless the interrupt
subroutine turns off (or masks) the control bits that enabled doze mode (MSR[WE], and HID0[DOZE]),
the device re-enters doze mode after the interrupt has been serviced. See
Power
The e500 core’s timer facilities are still enabled during doze mode, and core time base interrupts can be
generated. All device logic external to the core remains fully operational in doze mode.
19.5.1.5.2
In nap mode all clocks internal to the e500 core are turned off except for its timer facilities clock (the core
time base). The L1 caches do not respond to snoops in nap mode, so if coherency with external I/O
transactions is required, the L1 cache must be flushed before entering nap mode.
Similar to doze mode, interrupts occurring in nap mode cause the device to wake up the e500 core in order
to service the interrupt. However, unless the interrupt service routine changes the control bits that caused
the device to enter nap mode (MSR[WE], and HID0[NAP]), the MPC8533E returns to nap mode after the
interrupt is serviced. See
All device logic external to the e500 core remains fully operational in nap mode.
19.5.1.5.3
In sleep mode, all clocks internal to the e500 core are turned off, including the timer facilities clock. All
I/O interfaces in the device logic are also shut down. Only the clocks to the MPC8533E PIC are still
running so that an external interrupt can wake up the device.
After the core and I/O interfaces have shut down, ASLEEP is asserted and READY is negated.
19.5.1.6
The e500 core provides the following fields to signal power management requests to the MPC8533E
device logic.
19-28
•
•
Management,” for more information.
MSR[WE]—Used to qualify the values of HID0[DOZE,NAP,SLEEP] in the generation of the
internal doze, nap, and sleep signals.
HID0[DOZE]—Signals the MPC8533E to initiate doze mode.
Power Management Control Fields
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Doze Mode
Nap Mode
Sleep Mode
Only external interrupts can wake the MPC8533E from sleep mode. Internal
interrupt sources like the core interval timer or watchdog timer depend on
an active clock for their operation and these are disabled in sleep mode.
Section 19.5.1.8, “Interrupts and Power
NOTE
Section 10.1.3, “Interrupts to the Processor
Management,” for more information.
Section 19.5.1.8, “Interrupts and
Freescale Semiconductor
Core,”