MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 332

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DDR Memory Controller
1
9-10
0x140–
0x150–
0xBFC
0xE4C
Offset
0x08C
0x10C
0x11C
0x14C
0xBF4
0xBF8
0x080
0x084
0x088
0x100
0x104
0x108
0x110
0x114
0x118
0xE00
0xE04
0xE08
0xE20
0xE24
0xE28
0xE40
0xE44
0xE48
0xE50
0xE54
0xE58
0x120
0x124
0x128
0x130
0x144
0x148
Implementation-dependent reset values are listed in specified section/page.
CS0_CONFIG—Chip select 0 configuration
CS1_CONFIG—Chip select 1 configuration
CS2_CONFIG—Chip select 2 configuration
CS3_CONFIG—Chip select 3 configuration
TIMING_CFG_3—DDR SDRAM timing configuration 3
TIMING_CFG_0—DDR SDRAM timing configuration 0
TIMING_CFG_1—DDR SDRAM timing configuration 1
TIMING_CFG_2—DDR SDRAM timing configuration 2
DDR_SDRAM_CFG—DDR SDRAM control configuration
DDR_SDRAM_CFG_2—DDR SDRAM control configuration 2
DDR_SDRAM_MODE—DDR SDRAM mode configuration
DDR_SDRAM_MODE_2—DDR SDRAM mode configuration 2
DDR_SDRAM_MD_CNTL—DDR SDRAM mode control
DDR_SDRAM_INTERVAL—DDR SDRAM interval configuration
DDR_DATA_INIT—DDR SDRAM data initialization
DDR_SDRAM_CLK_CNTL—DDR SDRAM clock control
Reserved
DDR_INIT_ADDR—DDR training initialization address
DDR_INIT_EXT_ADDRESS—DDR training initialization extended
address
Reserved
DDR_IP_REV1—DDR IP block revision 1
DDR_IP_REV2—DDR IP block revision 2
DATA_ERR_INJECT_HI—Memory data path error injection mask high
DATA_ERR_INJECT_LO—Memory data path error injection mask low
ECC_ERR_INJECT—Memory data path error injection mask ECC
CAPTURE_DATA_HI—Memory data path read capture high
CAPTURE_DATA_LO—Memory data path read capture low
CAPTURE_ECC—Memory data path read capture ECC
ERR_DETECT—Memory error detect
ERR_DISABLE—Memory error disable
ERR_INT_EN—Memory error interrupt enable
CAPTURE_ATTRIBUTES—Memory error attributes capture
CAPTURE_ADDRESS—Memory error address capture
CAPTURE_EXT_ADDRESS—Memory error extended address capture
ERR_SBE—Single-Bit ECC memory error management
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 9-5. DDR Memory Controller Memory Map (continued)
Register
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
—
—
R
R
0x nnnn _ nnnn
0x00 nn _00 nn
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0011_0105
0x0000_0000
0x0000_0000
0x0200_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0200_0000
0x0000_0000
Reset
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Freescale Semiconductor
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9.4.1.15/9-30
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9.4.1.2/9-11
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9.4.1.7/9-20
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