MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 584

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
the internal bus, but also the system bus with the controller as bus master. Here are examples of the various
types of transfers:
12.6.2.1
The controller attempts to maximize use of the system bus by grouping outstanding bus requests from the
channels by request type (read or write). The controller performs all write requests to the internal system
bus, followed by all read requests, then repeat.
Within a request type, the controller grants bus access via the same snapshot scheme that is used for
granting EUs. If, for example, the controller is performing writes, it takes a snapshot of the current write
requests, satisfies them as the bus becomes available, then takes another snapshot of write requests, and
repeats. If there are no more write requests in a snapshot, the arbiter switches to handling reads. It
repeatedly takes snapshots of the reads waiting and satisfies them until there are no more read requests in
a snapshot. It then switches back to handling writes, etc.
As with arbitration for EUs, controls for setting channel priorities are in the master control register (see
Section 12.6.5.7, “Master Control Register
which request to satisfy within a snapshot. If both CHN3_BUS_PR_CNT and CHN4_BUS_PR_CNT are
set to non-zero values, the arbiter will implement the weighted priority scheme (see
“Channel Priority
“Channel Round-Robin
value results in unpredictable operation. When the buses are granted to a channel, they are granted until
the channel transfer is completely satisfied.
The SEC does not dynamically adjust its own transaction priorities. System software, however, can adjust
SEC transaction priority in real-time, with the change in priority taking effect immediately.
12-106
1. Obtaining a descriptor:
2. Transferring data length parameter from channel to EU
3. Obtaining input data from external memory for input to an EU
4. Writing output data from an EU back to external memory
— Channel makes request, arbitrates for attention from controller
— Controller arbitrates for use of the system bus and performs read from external memory
— Controller sends descriptor to channel over the internal bus
— Channel makes request, arbitrates for attention from controller
— Controller transfers data from channel to EU over the internal bus
— Channel makes request, arbitrates for attention from controller
— Controller arbitrates for use of the system bus and performs read from external memory
— Controller sends data to EU over the internal bus. If in-snooping, data is sent to two EUs
— Channel makes request, arbitrates for attention from controller
— Controller begins reading data from the EU into a controller FIFO. If out-snooping, the same
— Controller performs write to external memory
data is also read by another EU. Meanwhile, the controller arbitrates for use of the internal
system bus.
Arbitration for Use of the Controller and Buses
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Arbitration”). If both are zero, the arbitration will be round-robin (see
Arbitration”). Setting only one of the CHNx_BUS_PR_CNT fields to a non-zero
(MCR)”), and the same two methods are available for selecting
Freescale Semiconductor
Section 12.6.1.1,
Section 12.6.1.2,