MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 21

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Paragraph
Number
12.4.6.6
12.4.6.7
12.4.6.8
12.4.6.9
12.4.6.9.1
12.4.6.9.2
12.4.6.9.3
12.4.6.9.4
12.4.6.9.5
12.4.6.9.6
12.4.7
12.4.7.1
12.4.7.2
12.4.7.3
12.4.7.4
12.4.7.5
12.4.7.6
12.4.7.7
12.4.7.8
12.4.7.9
12.4.7.10
12.4.7.11
12.4.7.12
12.4.7.13
12.4.7.14
12.4.7.15
12.4.7.16
12.5
12.5.1
12.5.1.1
12.5.1.2
12.5.1.3
12.5.1.4
12.5.1.5
12.5.1.6
12.5.2
12.5.2.1
12.5.2.2
12.5.2.3
12.6
12.6.1
Freescale Semiconductor
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Crypto-Channels .......................................................................................................... 12-91
Security Controller..................................................................................................... 12-104
Kasumi Execution Unit (KEU)................................................................................ 12-79
Channel Registers .................................................................................................... 12-92
Channel Interrupts.................................................................................................. 12-103
Assignment of EUs to Channels ............................................................................ 12-104
AESU Interrupt Status Register (AESUISR)....................................................... 12-72
AESU Interrupt Control Register (AESUICR).................................................... 12-73
AESU EU Go Register (AESUEUG) .................................................................. 12-74
AESU Context Registers ..................................................................................... 12-75
KEU Mode Register (KEUMR) .......................................................................... 12-80
KEU Key Size Register (KEUKSR).................................................................... 12-81
KEU Data Size Register (KEUDSR)................................................................... 12-81
KEU Reset Control Register (KEURCR)............................................................ 12-82
KEU Status Register (KEUSR) ........................................................................... 12-83
KEU Interrupt Status Register (KEUISR) ........................................................... 12-84
KEU Interrupt Control Register (KEUICR) ........................................................ 12-85
KEU Data Out Register (F9 MAC) (KEUDOR) ................................................. 12-87
KEU EU Go Register (KEUEUG) ...................................................................... 12-87
KEU IV 1 Register (KEUIV1) ............................................................................ 12-88
KEU ICV_In Register (KEUICV)....................................................................... 12-88
KEU IV_2 Register (Fresh) (KEUIV2) ............................................................... 12-89
KEU Context Data Registers (KEUCn) .............................................................. 12-89
KEU Key Data Registers_1 and _2 (Confidentiality Key) (KEUKDn) .............. 12-89
KEU Key Data Registers _3 and _4 (Integrity Key) (KEUKDn) ....................... 12-90
KEU FIFOs .......................................................................................................... 12-90
Crypto-Channel Configuration Registers 1–4 (CCCRn) ..................................... 12-92
Crypto-Channel Pointer Status Registers 1–4 (CCPSRn) ................................... 12-95
Crypto-Channel Current Descriptor Pointer Registers 1–4 (CCDPRn) ............ 12-100
Fetch FIFO Address Registers 1–4 (FFn).......................................................... 12-101
Crypto-Channel 1–4 Descriptor Buffers [0–7] (DBn[0–7]) .............................. 12-102
Link Table Buffer Registers (Scatter or Gather)—LTB0–3 .............................. 12-102
Channel Done Interrupt ..................................................................................... 12-103
Channel Error Interrupt...................................................................................... 12-103
Channel Reset .................................................................................................... 12-103
Context for CBC Mode.................................................................................... 12-76
Context for Counter Mode............................................................................... 12-76
Context for SRT Mode .................................................................................... 12-76
Context for CCM Mode................................................................................... 12-77
AESU Key Registers ....................................................................................... 12-79
AESU FIFOs.................................................................................................... 12-79
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