MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 12

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Paragraph
Number
7.3.1.4
7.3.1.4.1
7.3.1.4.2
7.4
7.4.1
7.5
7.6
7.6.1
7.6.2
7.7
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.7.6
7.8
7.8.1
7.8.2
7.9
7.9.1
7.9.1.1
7.9.1.2
7.9.2
7.9.3
7.9.3.1
7.9.3.2
7.9.4
7.9.5
7.9.6
8.1
8.1.1
8.1.2
8.2
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MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
External Writes to the L2 Cache (Cache Stashing)........................................................ 7-25
L2 Cache Timing ........................................................................................................... 7-27
L2 Cache and SRAM Coherency................................................................................... 7-27
L2 Cache Locking.......................................................................................................... 7-29
PLRU L2 Replacement Policy....................................................................................... 7-31
L2 Cache Operation ....................................................................................................... 7-33
Introduction...................................................................................................................... 8-1
Memory Map/Register Definition ................................................................................... 8-3
Stash-Only Cache Regions ........................................................................................ 7-26
L2 Cache Coherency Rules........................................................................................ 7-28
Memory-Mapped SRAM Coherency Rules .............................................................. 7-29
Locking the Entire L2 Cache ..................................................................................... 7-29
Locking Programmed Memory Ranges..................................................................... 7-30
Locking Selected Lines.............................................................................................. 7-30
Clearing Locks on Selected Lines ............................................................................. 7-30
Flash Clearing of Instruction and Data Locks ........................................................... 7-31
Locks with Stale Data ................................................................................................ 7-31
PLRU Bit Update Considerations.............................................................................. 7-32
Allocation of Lines .................................................................................................... 7-32
Initialization ............................................................................................................... 7-33
Flash Invalidation of the L2 Cache............................................................................ 7-34
Managing Errors ........................................................................................................ 7-34
L2 Cache States ......................................................................................................... 7-34
L2 State Transitions ................................................................................................... 7-35
Error Checking and Correcting (ECC) ...................................................................... 7-39
Overview...................................................................................................................... 8-2
Features........................................................................................................................ 8-2
L2 Error Registers.................................................................................................. 7-17
L2 Cache Initialization .......................................................................................... 7-33
Memory-Mapped SRAM Initialization ................................................................. 7-33
ECC Errors............................................................................................................. 7-34
Tag Parity Errors.................................................................................................... 7-34
Error Injection Registers.................................................................................... 7-18
Error Control and Capture Registers ................................................................. 7-20
Memory, Security, and I/O Interfaces
e500 Coherency Module
Contents
Chapter 8
Part III
Title
Freescale Semiconductor
Number
Page