MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 1087

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Table 18-30
inbound transaction from an external source.
18.3.6.7
Together with the other PCI Express error capture registers, PEX_ERR_CAP_R2 allows vital error
information to be captured when an error occurs. Different error information is reported depending on
whether the error source is from an outbound transaction from an internal source or from an inbound
transaction from an external source; the source of the captured error is reflected in
PEX_ERR_CAP_STAT[GSID]. Note that after the initial error is captured, no further capturing is
performed until the PEX_ERR_CAP_STAT[ECV] bit is clear.
PEX_ERR_CAP_R2 for the case when the error is caused by an outbound transaction from an internal
source (that is, PEX_ERR_CAP_STAT[GSID] ≠ 0h02), is shown in
Freescale Semiconductor
Offset 0xE30
Reset
W
R
0
0–31 GH1
describes the fields of PEX_ERR_CAP_R1 for the case when the error is caused by an
Bits Name
PCI Express Error Capture Register 2 (PEX_ERR_CAP_R2)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure 18-32. PCI Express Error Capture Register 2 (PEX_ERR_CAP_R2)
Table 18-30. PCI Express Error Capture Register 1 Field Descriptions
PEX 2nd DW (4-byte) header. This field contains the PCI Express error packet’s 2nd
DW (4-byte) header.
24–31
16–23
13–15
12
8–11
0–7
Comp ID[15:8]
Comp ID[7:0]
Comp Status
BCM
Byte Count[11:8]
Byte Count[7:0]
Internal Source, Outbound Transaction
External Source, Inbound Transaction
All zeros
Description
OD1
Figure
18-32.
PCI Express Interface Controller
Access: Read/Write
18-39
31