MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 794

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
15.5.3.4
This section describes the MAC registers and provides a brief overview of the functionality that can be
exercised through the use of these registers, particularly those that provide functionality not explicitly
required by the IEEE 802.3 standard. All of the MAC registers are 32 bits wide.
15.5.3.4.1
The MAC configuration registers 1 and 2 provide for configuring the MAC in multiple ways:
15.5.3.4.2
The half-duplex register (HAFDUP) allows control over the carrier-sense multiple access/collision
detection (CSMA/CD) logic of the eTSEC. Half-duplex mode is only supported for 10- and 100-Mbps
operation. Following the completion of the packet transmission the part begins timing the inter packet gap
(IPG) as programmed in the back-to-back IPG configuration register. The system is now free to begin
another frame transfer.
In full-duplex mode both the carrier sense (CRS) and collision (COL) indications from the PHY are
ignored, but in half-duplex mode the eTSEC defers to CRS, and following a carrier event, times the IPG
using the non-back-to-back IPG configuration values that include support for the optional
two-thirds/one-third CRS deferral process. This optional IPG mechanism enhances system robustness and
ensures fair access to the medium. During the first two-thirds of the IPG, the IPG timer is cleared if CRS
is sensed. During the final one-third of the IPG, CRS is ignored and the transmission begins once IPG is
timed. The two-thirds/one-third ratio is the recommended value.
15.5.3.4.3
While transmitting a packet in half-duplex mode, the eTSEC is sensitive to COL. If a collision occurs, it
aborts the packet and outputs the 32-bit jam sequence. The jam sequence is comprised of several bits of
the CRC, inverted to guarantee an invalid CRC upon reception. A signal is sent to the system indicating
that a collision occurred and that the start of the frame is needed for retransmission. The eTSEC then backs
off of the medium for a time determined by the truncated binary exponential back off (BEB) algorithm.
Following this back-off time, the packet is retried. The back-off time can be skipped if configured via the
half-duplex register. However, this is non-standard behavior and its use must be carefully applied. Should
any one packet experience excessive collisions, the packet is aborted. The system should flush the frame
and move to the next one in line. If the system requests to send a packet while the eTSEC is deferring to a
15-64
•
•
Adjusting the preamble length—The length of the preamble can be adjusted from the nominal
seven bytes to some other (non-zero) value. Should custom preamble insertion/extraction be
configured, then this register must by left at its default value.
Varying pad/CRC combinations—Three different pad/CRC combinations are provided to handle a
variety of system requirements. Simplest are frames that already have a valid frame check
sequence (FCS) field. The other two options include appending a valid CRC or padding and then
appending a valid CRC, resulting in a minimum frame of 64 octets. In addition to the
programmable register set, the pad/CRC behavior can be dynamically adjusted on a per-packet
basis.
MAC Functionality
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Configuring the MAC
Controlling CSMA/CD
Handling Packet Collisions
Freescale Semiconductor