MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 600

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DUART
13.3.1
The following sections describe the UART0 and UART1 registers.
13.3.1.1
These registers contain the data received from the transmitter on the UART buses. In FIFO mode, when
read, they return the first byte received. For FIFO status information, refer to the UDSR[RXRDY]
description.
Except for the case when there is an overrun, URBR returns the data in the order it was received from the
transmitter. Refer to the ULSR[OE] description,
ULSR1).” Figure 13-3
UTHRs.
Figure 13-2
Table 13-4
13.3.1.2
A write to these 8-bit registers causes the UART devices to transfer 5–8 data bits on the UART bus in the
format set up in the ULCR (line control register). In FIFO mode, data written to UTHR is placed into the
FIFO. The data written to UTHR is the data sent onto the UART bus, and the first byte written to UTHR
will be the first byte onto the bus. UDSR[TXRDY] indicates when the FIFO is full. Refer to the
Table 13-21
13-6
Bits
0–7
Offset 0x500
Reset
Name
DATA
W
R
describes the fields of URBR.
shows the bits in the URBRs.
0x600
and the
Register Descriptions
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Data received from the transmitter on the UART bus (read only)
Receiver Buffer Registers (URBR0, URBR1) (ULCR[DLAB] = 0)
Transmitter Holding Registers (UTHR0, UTHR1) (ULCR[DLAB] = 0)
0
Table 13-22
shows the receiver buffer registers. Note that these registers have same offset as the
Figure 13-2. Receiver Buffer Registers (URBR0, URBR1)
for more details.
Table 13-4. URBR Field Descriptions
Section 13.3.1.9, “Line Status Registers (ULSR0,
All zeros
Description
Freescale Semiconductor
Access: Read only
7