MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 717

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MPC8533EVTALFA

Manufacturer Part Number
MPC8533EVTALFA
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTALFA

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
783-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8533EVTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
The read and write strobes are also used as the data latch control to complete the bus transactions, obviating
the need for any handshake termination signal from the DSP. The UPM programmer is responsible for
satisfying the AC timings of the HDI16 transactions.
Through appropriate mode selection, the HDI16 peripheral’s feature set can be fully supported by the local
bus’s UPM controlled signals. The UPM defined interface can be used with any of the local bus’s eight
chip selects to give the 16-bit port size and strobe generation that matches that of the HDI16 host port.
Figure 14-80
14.5.6.1.2
The physical interconnections between the UPM controlled local bus and the HDI16 of the MSC8101
HDI16 peripheral are given in
Freescale Semiconductor
shows the internal register diagram of the HDI16.
HCR
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
ISR
MSC8101
Signal(s)
HD[0:15]
HRDRW
Physical Interconnections
16
16
HCS1
HCS2
HA[0]
HA[1]
HA[2]
HA[3]
HSR
ICR
16
16
Table 14-44. Local Bus to MSC8101 HDI16 Connections
Figure 14-80. MSC8101 HDI16 Peripheral Registers
HCVR
Type
I/O/Z
CVR
Table 14-44
I
I
I
I
I
I
I
16
16
Host data bus
Host address line
Host address line
Host address line
Host address line
Host chip select 1
Host chip select 2
Host R/W signal
HPCR
16
RX0
16
and
Description
DMA Data Bus
RX1
64
Figure
Host Bus
HOTX
16
RX2
14-81.
64
16
QBus Data Bus
RX3
16
LAD[0:15]
Either LA[27] or latched A25
Either LA[28] or latched A26
LCS n
Tie this to V
LGPL1 or inverted LBCTL signal
Connect with Local Bus Signal
LA[29]
LA[30]
TX0
16
DD
TX1
64
HORX
16
TX2
64
16
TX3
Local Bus Controller
16
14-99

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