MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 345

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

9.4.1.8
The DDR SDRAM control configuration register 2, shown in
configuration for the DDR controller.
Freescale Semiconductor
Offset 0x114
Reset
Reset All zeros
Bits
30
31
W
W
R
R
FRC_SR SR_IE DLL_RST_DIS — DQS_CFG
MEM_HALT
16
0
Name
Figure 9-9. DDR SDRAM Control Configuration Register 2 (DDR_SDRAM_CFG_2)
BI
DDR SDRAM Control Configuration 2 (DDR_SDRAM_CFG_2)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
1
NUM_PR
Table 9-12. DDR_SDRAM_CFG Field Descriptions (continued)
read/write transactions to DDR SDRAM until the bit is cleared again. This can be used when
bypassing initialization and forcing MODE REGISTER SET commands through software.
0 DDR controller will accept new transactions.
1 DDR controller will finish any remaining transactions, and then it will remain halted until this bit is
Bypass initialization
0 DDR controller will cycle through initialization routine based on SDRAM_TYPE
1 Initialization routine will be bypassed. Software is responsible for initializing memory through
See
errors in this mode.
DDR memory controller halt. When this bit is set, the memory controller will not accept any new data
cleared by software.
DDR_SDRAM_MODE2 register. If software is initializing memory, then the MEM_HALT bit can be
set to prevent the DDR controller from issuing transactions during the initialization sequence.
Note that the DDR controller will not issue a DLL reset to the DRAMs when bypassing the
initialization routine, regardless of the value of DDR_SDRAM_CFG[DLL_RST_DIS]. If a DLL
reset is required, then the controller should be forced to enter and exit self refresh after the
controller is enabled.
Section 9.4.1.15, “DDR Initialization Address (DDR_INIT_ADDR),”
2
19
3
20
4
5
6
All zeros
—
8
—
Description
Figure
ODT_CFG
9
9-9, provides more control
10
26
D_INIT
11
27
for details on avoiding ECC
DDR Memory Controller
28
Access: Read/Write
—
—
9-23
15
31