MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 555

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

12.4.6.9.4
The SEC AESU is capable of performing single pass encryption and MAC generation. The host is required
to order the CCM context is such a way that the context can be fetched as a contiguous string into the
context registers, prior to encryption/MAC generation or decryption/MAC validation. The context register
contents for CCM mode is summarized in
The context for CCM encryption/MAC generation is:
Note: The counter modulus for CCM mode is currently defined as 2
value has been made programmable in the SEC in case the final version of 802.11i uses a different counter
modulus. Because this is a programmable field, it must be generated and stored along with other
session-specific information for loading into the AESU context register prior to CCM encryption.
CCM encryption processing
With the session-specific key and context, the AESU performs the following operations.
Freescale Semiconductor
Encrypt
(outbound
Decrypt
(inbound)
•
•
•
•
1. Initialize the IV, and encrypt with the symmetric key.
2. In CBC fashion, take the output of step 1, hash with the first block of plaintext, and encrypt with
3. Continue as in step 2 until the final block of plaintext has been processed. The result of the
4. The first item to be encrypted in counter mode is the counter (initial counter value) from context
Reg 1–2 Session-specific 128-bit initialization vector (from memory)
Reg 3–4 128 bits of zero padding
Reg 5–6 Session-specific counter (initial counter value) (from memory)
Reg 7 Counter modulus exponent (msb<--lsb); should be fixed at 0x0000_0080.
the symmetric key.
encryption of the final block of plaintext with the symmetric key is the MAC tag. The full 128 bits
of MAC data is written to context registers 1–2, for use in the next phase of CCM processing.
Once the MAC Tag has been generated (step 3), the MAC tag, along with the plaintext is encrypted
with the AESU operating in counter mode.
registers 5–6. The counter is encrypted with the symmetric key, and the result is hashed with the
MAC tag (retrieved from context register1–2) to produce the MIC (encrypted MAC), which is then
stored in context registers 3–4. At the completion of CCM encrypt processing, this MIC is output
Inputs
Outputs
Inputs
Outputs
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Context for CCM Mode
Computed
MAC
MAC
1
IV
IV
Figure 12-56. AESU CCM Context Registers
0
0
2
Figure 12-56
Decrypted
MAC
MIC
MIC
3
Context Registers
0
and further described below.
0
0
0
4
128
5
Initial Counter
Initial Counter
, making the exponent 128. This
6
Security Engine (SEC) 2.1
Counter Modulus
Counter Modulus
Exponent
Exponent
7
12-77