XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 106

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Spartan-3 FPGA Family: Pinout Descriptions
Table 70: Dual-Purpose Pins Used in Master or Slave Serial Mode
Parallel Configuration Modes (SelectMAP)
This section describes the dual-purpose configuration pins
used during the Master and Slave Parallel configuration
modes, sometimes also called the SelectMAP modes. In
both Master and Slave Parallel configuration modes, D0-D7
form the byte-wide configuration data input. See
for Mode Select pin settings required for Parallel modes.
106
DIN
DOUT
INIT_B
Pin Name
Configuration Data Byte
Bidirectional
(open-drain)
Direction
Output
Input
0xFC =
Figure 39: Configuration Data Byte Mapping to D0-D7 Bits
Serial Data Input:
During the Master or Slave Serial configuration modes, DIN is the serial configuration data
input, and all data is synchronized to the rising CCLK edge. After configuration, this pin is
available as a user I/O.
This signal is located in Bank 4 and its output voltage determined by VCCO_4.
The BitGen option Persist permits this pin to retain its configuration function in the User
mode.
Serial Data Output:
In a multi-FPGA design where all the FPGAs use serial mode, connect the DOUT output of
one FPGA—in either Master or Slave Serial mode—to the DIN input of the next FPGA—in
Slave Serial mode—so that configuration data passes from one to the next, in daisy-chain
fashion. This “daisy chain” permits sequential configuration of multiple FPGAs.
This signal is located in Bank 4 and its output voltage determined by VCCO_4.
The BitGen option Persist permits this pin to retain its configuration function in the User
mode.
Initializing Configuration Memory/Configuration Error:
Just after power is applied, the FPGA produces a Low-to-High transition on this pin
indicating that initialization (i.e., clearing) of the configuration memory has finished. Before
entering the User mode, this pin functions as an open-drain output, which requires a pull-up
resistor in order to produce a High logic level. In a multi-FPGA design, tie (wire AND) the
INIT_B pins from all FPGAs together so that the common node transitions High only after
all of the FPGAs have been successfully initialized.
Externally holding this pin Low beyond the initialization phase delays the start of
configuration. This action stalls the FPGA at the configuration step just before the mode
select pins are sampled.
During configuration, the FPGA indicates the occurrence of a data (i.e., CRC) error by
asserting INIT_B Low.
This signal is located in Bank 4 and its output voltage determined by VCCO_4.
The BitGen option Persist permits this pin to retain its configuration function in the User
mode.
(MSB)
D0
1
I/O Bank 4 (VCCO_4)
Table 74
High Nibble
D1
1
www.xilinx.com
D2
1
As shown in
D7 is the least-significant bit. Bits D0-D3 form the high nib-
ble of the byte and bits D4-D7 form the low nibble.
In the Parallel configuration modes, both the VCCO_4 and
VCCO_5 voltage supplies are required and must both equal
the voltage of the attached configuration device, typically
either 2.5V or 3.3V.
D3
1
Description
Figure
D4
1
I/O Bank 5 (VCCO_5)
39, D0 is the most-significant bit while
D5
Low Nibble
1
DS099-4 (v2.2) May 25, 2007
D6
0
Product Specification
(LSB)
D7
0
R