XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 107

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Assert Low both the chip-select pin, CS_B, and the
read/write control pin, RDWR_B, to write the configuration
data byte presented on the D0-D7 pins to the FPGA on a
rising-edge of the configuration clock, CCLK. The order of
CS_B and RDWR_B does not matter, although RDWR_B
must be asserted throughout the configuration process. If
RDWR_B is de-asserted during configuration, the FPGA
aborts the configuration operation.
After configuration, these pins are available as general-pur-
pose user I/O. However, the SelectMAP configuration inter-
face is optionally available for debugging and dynamic
Table 71: Dual-Purpose Configuration Pins for Parallel (SelectMAP) Configuration Modes
DS099-4 (v2.2) May 25, 2007
Product Specification
D0,
D1,
D2,
D3
D4,
D5,
D6,
D7
CS_B
Name
Pin
R
Output during
Output during
configuration
configuration
Input during
Input during
Direction
readback
readback
Input
Configuration Data Port (high nibble):
Collectively, the D0-D7 pins are the byte-wide configuration data port for the Parallel
(SelectMAP) configuration modes. Configuration data is synchronized to the rising edge of
CCLK clock signal.
The D0-D3 pins are the high nibble of the configuration data byte and located in Bank 4 and
powered by VCCO_4.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
Configuration Data Port (low nibble):
The D4-D7 pins are the low nibble of the configuration data byte. However, these signals are
located in Bank 5 and powered by VCCO_5.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
Chip Select for Parallel Mode Configuration:
Assert this pin Low, together with RDWR_B to write a configuration data byte from the D0-D7
bus to the FPGA on a rising CCLK edge.
During Readback, assert this pin Low, along with RDWR_B High, to read a configuration data
byte from the FPGA to the D0-D7 bus on a rising CCLK edge.
This signal is located in Bank 5 and powered by VCCO_5.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
CS_B
0
1
FPGA selected. SelectMAP inputs are valid on the next rising edge of CCLK.
FPGA deselected. All SelectMAP inputs are ignored.
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reconfiguration. To use these SelectMAP pins after configu-
ration, set the Persist bitstream generation option.
The Readback debugging option, for example, requires the
Persist bitstream generation option. During Readback
mode, assert CS_B Low, along with RDWR_B High, to read
a configuration data byte from the FPGA to the D0-D7 bus
on a rising CCLK edge. During Readback mode, D0-D7 are
output pins.
In all the cases, the configuration data and control signals
are synchronized to the rising edge of the CCLK clock sig-
nal.
Description
Spartan-3 FPGA Family: Pinout Descriptions
Function
107