XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 140

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Spartan-3 FPGA Family: Pinout Descriptions
140
PQ208 Footprint
Left Half of Package
(top view)
XC3S50
(124 max. user I/O)
XC3S200, XC3S400
(141 max user I/O)
All devices
72
16
17
83
22
12
16
12
28
0
8
7
4
4
8
Figure 45: PQ208 Package Footprint (top view). Note pin 1 indicator in top-left corner and logo orientation.
I/O: Unrestricted,
general-purpose user I/O
VREF: User I/O or input
voltage reference for bank
N.C.: Unconnected pins for
XC3S50 ( )
I/O: Unrestricted,
general-purpose user I/O
VREF: User I/O or input
voltage reference for bank
N.C.: No unconnected pins
in this package
DUAL: Configuration pin,
then possible user I/O
GCLK: User I/O or global
clock buffer input
DCI: User I/O or reference
resistor input for bank
CONFIG: Dedicated
configuration pins
JTAG: Dedicated JTAG
port pins
VCCINT: Internal core
voltage supply (+1.2V)
VCCO: Output voltage
supply for bank
VCCAUX: Auxiliary voltage
supply (+2.5V)
GND: Ground
( ) IO_L16P_7/VREF_7
IO_L19N_7/VREF_7
IO_L40N_7/VREF_7
IO_L24N_6/VREF_6
IO_L40P_6/VREF_6
IO_L01P_7/VRN_7
IO_L01N_7/VRP_7
IO_L01N_6/VRP_6
IO_L01P_6/VRN_6
( ) IO/VREF_6
( ) IO_L16N_7
( ) IO_L39N_7
( ) IO_L39N_6
( ) IO_L39P_7
( ) IO_L39P_6
IO_L22N_7
IO_L19P_7
IO_L20P_7
IO_L21P_7
IO_L22P_7
IO_L23P_7
IO_L23N_7
IO_L24P_7
IO_L24N_7
IO_L40P_7
IO_L40N_6
IO_L24P_6
IO_L23P_6
IO_L23N_6
IO_L22P_6
IO_L22N_6
IO_L21P_6
IO_L21N_6
IO_L20P_6
IO_L20N_6
IO_L19P_6
IO_L19N_6
IO_L20N_7
IO_L21N_7
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VCCA X
VCCAUX
VCCO_7
VCCO_7
VCCO_6
VCCO_6
GND
GND
GND
GND
GND
GND
GND
U
52
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
1
3
4
5
6
7
8
9
2
Bank 0
Bank 5
DS099-4 (v2.2) May 25, 2007
Product Specification
DS099-4_09a_121103
R