XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 54

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Spartan-3 FPGA Family: Functional Description
Revision History
54
54
04/11/03
05/19/03
07/11/03
08/24/04
08/19/05
04/03/06
04/26/06
05/25/07
Date
Version No.
1.0
1.1
1.2
1.3
1.4
2.0
2.1
2.2
Initial Xilinx release
Added Block RAM column, DCMs, and multipliers to XC3S50 descriptions.
Explained the configuration port Persist option in
Updated
for the XC3S50 is the same as that for all other Spartan-3 devices. Updated description of I/O
voltage tolerance in
DCI version of the LVCMOS standard to None. Added additional flexibility for making DLL
connections in
explanation of how to choose power supplies for the configuration interface, including
guidelines for achieving 3.3V-tolerance.
Showed inversion of 3-state signal
resistors
page
synchronized to CCLK
Corrected description of WRITE_FIRST and READ_FIRST in
address setup and hold time requirements whenever a block RAM port is enabled
Added information in the maximum length of a
to
STATUS[2] DCM output
recommendations to Configuration. Added
Added
timing is not programmable.
Updated
Platform Flash supply voltage name and value in
Charge Pumps or Free-Running
Added more information on the pull-up resistors that are active during configuration to
Configuration. Added information to
interactions when configuring via JTAG if the mode select pins are set for other than JTAG.
Added
25-Ohm driver in
scan tests.
XAPP453
25. Corrected output buffer name in
Powering Spartan-3 FPGAs
New Spartan-3 Generation Design Documentation
Figure 6
(Table 5
Figure
in
3.3V-Tolerant Configuration Interface
Figure 19
5. Updated
Table 9
and
and
ESD Protection
Double-Data-Rate Transmission
page
(page
(Table
www.xilinx.com
and accompanying text. In the
and
15). Added information on operating block RAM with multipliers to
Figure
46).
Table
22). Added information on CCLK behavior and termination
Oscillators. Corrected a few minor typographical errors.
12. Updated
(Figure
10. Added note that pull-down is active during boundary
section. Removed GSR from
section. In
Boundary-Scan (JTAG) Mode
Description
Figure
5). Clarified description of pull-up and pull-down
Additional Configuration Details
Configuration
Table
Table
Figure 24
Slave Parallel Mode (SelectMAP)
19. Corrected description of how DOUT is
9. Updated
9, changed input termination type for
section. Added information on the
Configuration
section to indicate that DDR clocking
and
Available. Noted SSTL2_I_DCI
Table
daisy-chain. Added reference
Figure
Figure
Figure 29
DS099-2 (v2.2) May 25, 2007
12. Added note regarding
about potential
26. Added
section, inserted an
20. Corrected
Product Specification
because its
section.
No Internal
(Table
section.
12).
R