XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 45

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Configuration
Spartan-3 devices are configured by loading application
specific configuration data into the internal configuration
memory. Configuration is carried out using a subset of the
device pins, some of which are "Dedicated" to one function
only, while others, indicated by the term "Dual-Purpose",
Table 25: Spartan-3 Configuration Mode Pin Settings
The HSWAP_EN input pin defines whether the I/O pins that
are not actively used during configuration have pull-up
resistors during configuration. By default, HSWAP_EN is
tied High (via an internal pull-up resistor if left floating) which
shuts off the pull-up resistors on the user I/O pins during
configuration. When HSWAP_EN is tied Low, user I/Os
have pull-ups during configuration. The Dedicated configu-
ration pins (CCLK, DONE, PROG_B, M2, M1, M0,
HSWAP_EN) and the JTAG pins (TDI, TMS, TCK, and
TDO) always have a pull-up resistor to VCCAUX during
configuration, regardless of the value on the HSWAP_EN
pin. Similarly, the Dual-prupose INIT_B pin has an internal
pull-up resistor to VCCO_4 or VCCO_BOTTOM, depending
on the package style.
Depending on the chosen configuration mode, the FPGA
either generates a CCLK output, or CCLK is an input
accepting an externally generated clock.
A persist option is available which can be used to force the
configuration pins to retain their configuration function even
after device configuration is complete. If the persist option is
not selected then the configuration pins with the exception
of CCLK, PROG_B, and DONE can be used as user I/O in
normal operation. The persist option does not apply to the
boundary-scan related pins. The persist feature is valuable
in applications that readback configuration data after enter-
ing the User mode.
Table 26
each FPGA as well as the PROMs suitable for storing those
bits. See
Configuration PROMs data sheet for more information.
The maximum bitstream length that Spartan-3 FPGAs sup-
port in serial daisy-chains is 4,294,967,264 bits (4 Gbits),
roughly equivalent to a daisy-chain with 323 XC3S5000
FPGAs. This is a limit only for serial daisy-chains where
DS099-2 (v2.2) May 25, 2007
Product Specification
Notes:
1.
2.
Master Serial
Slave Serial
Master Parallel
Slave Parallel
JTAG
Configuration Mode
The voltage levels on the M0, M1, and M2 pins select the configuration mode.
The daisy chain is possible only in the Serial modes when DOUT is used.
lists the total number of bits required to configure
DS123
R
: Platform Flash In-System Programmable
(1)
M0
0
1
1
0
1
M1
0
1
1
1
0
M2
0
1
0
1
1
www.xilinx.com
Synchronizing Clock
CCLK Output
CCLK Output
CCLK Input
CCLK Input
TCK Input
can be re-used as general-purpose User I/Os once configu-
ration is complete.
Depending on the system design, several configuration
modes are supported, selectable via mode pins. The mode
pins M0, M1, and M2 are Dedicated pins. The mode pin set-
tings are shown in
configuration data is passed via the FPGA’s DOUT pin.
There is no such limit for JTAG chains.
The Standard Configuration Interface
Configuration signals belong to one of two different catego-
ries: Dedicated or Dual-Purpose. Which category deter-
mines which of the FPGA’s power rails supplies the signal’s
driver and, thus, helps describe the electrical at the pin.
The Dedicated configuration pins include PROG_B,
HSWAP_EN, TDI, TMS, TCK, TDO, CCLK, DONE, and
M0-M2. These pins are powered by the V
Table 26: Spartan-3 Configuration Data
The Dual-Purpose configuration pins comprise INIT_B,
DOUT, BUSY, RDWR_B, CS_B, and DIN/D0-D7. Each of
these pins, according to its bank placement, uses the V
lines for either Bank 4 (VCCO_4 on most packages,
VCCO_BOTTOM on TQ144 and CP132 packages) or Bank
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S200
XC3S400
XC3S50
Device
Spartan-3 FPGA Family: Functional Description
11,316,864
13,271,936
File Sizes
1,047,616
1,699,136
3,223,488
5,214,784
7,673,024
439,264
Table
Data Width
25.
1
1
8
8
1
Configuration
Xilinx Platform Flash PROM
XCF01S
XCF01S
XCF02S
XCF04S
XCF08P
XCF08P
XCF16P
XCF16P
Serial
Serial DOUT
CCAUX
Configuration
Yes
Yes
No
No
No
XCF08P
XCF08P
XCF08P
XCF08P
XCF08P
XCF08P
XCF16P
XCF16P
Parallel
supply.
(2)
CCO
45