XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 46

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Spartan-3 FPGA Family: Functional Description
5 (VCCO_5). All the signals used in the serial configuration
modes rely on VCCO_4 power. Signals used in the parallel
configuration modes and Readback require from VCCO_5
as well as from VCCO_4.
Both the Dedicated signals described above and the
Dual-Purpose signals constitute the configuration interface.
The Dedicated pins, powered by the 2.5V V
always use the LVCMOS25 I/O standard. The Dual-Pur-
pose signals, however, are powered by the VCCO_4 supply
and also by the VCCO_5 supply in the Parallel configuration
modes. The simplest configuration interface uses 2.5V for
VCCO_4 and VCCO_5, if required. However, VCCO_4 and,
if needed, VCCO_5 can be voltages other than 2.5V but
then the configuration interface will have two voltage levels:
2.5V for V
Dual-Purpose signals default to the LVCMOS input and out-
put levels for the associated V
3.3V-Tolerant Configuration Interface
A 3.3V-tolerant configuration interface simply requires add-
ing a few external resistors as described in detail in "The
3.3V Configuration of Spartan-3 FPGAs" (
The 3.3V-tolerance is implemented as follows (a similar
approach can be used for other supply voltage levels):
Apply 3.3V to VCCO_4 and, in some configuration modes,
to VCCO_5 to power the Dual-Purpose configuration pins.
This scales the output voltages and input thresholds associ-
ated with these pins so that they become 3.3V-compatible.
Apply 2.5V to V
pins. For 3.3V-tolerance, the Dedicated inputs require
46
54
CCAUX
CCAUX
and a separate V
to power the Dedicated configuration
CCO
voltage supply.
CCO
XAPP453
CCAUX
supply. The
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supply,
www.xilinx.com
series resistors to limit the incoming current to 10 mA or
less. The Dedicated outputs have reduced noise margin
when the FPGA drives a High logic level into another
device’s 3.3V receiver. Choose a power regulator or supply
that can tolerate reverse current on the V
Configuration Modes
Spartan-3 supports the following five configuration modes:
•
•
•
•
•
Slave Serial Mode
In Slave Serial mode, the FPGA receives configuration data
in bit-serial form from a serial PROM or other serial source
of configuration data. The FPGA on the far right of
Figure 24
the FPGA is an input in this mode. The serial bitstream must
be set up at the DIN input pin a short time before each rising
edge of the externally generated CCLK.
Multiple FPGAs can be daisy-chained for configuration from
a single source. After a particular FPGA has been config-
ured, the data for the next device is routed internally to the
DOUT pin. The data on the DOUT pin changes on the falling
edge of CCLK.
Slave Serial mode
Master Serial mode
Slave Parallel
Master Parallel (SelectMAP) mode
Boundary-Scan (JTAG) mode (IEEE 1532/IEEE
1149.1)
is set for the Slave Serial mode. The CCLK pin on
(SelectMAP)
DS099-2 (v2.2) May 25, 2007
mode
Product Specification
CCAUX
lines.
R