XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 153

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

FG456: 456-lead Fine-pitch Ball Grid
Array
The 456-lead fine-pitch ball grid array package, FG456,
supports four different Spartan-3 devices, including the
XC3S400, the XC3S1000, the XC3S1500, and the
XC3S2000. The footprints for the XC3S1000, the
XC3S1500, and the XC3S2000 are identical, as shown in
Table 99
I/O pins which consequently results in 69 unconnected pins
on the FG456 package, labeled as “N.C.” In
Figure
black diamond symbol ( ).
All the package pins appear in
bank number, then by pin name. Pairs of pins that form a
differential I/O pair appear together in the table. The table
also shows the pin number for each pin and the pin type, as
defined earlier.
If there is a difference between the XC3S400 pinout and the
pinout for the XC3S1000, the XC3S1500, or the XC3S2000,
then that difference is highlighted in
entry is shaded grey, then there is an unconnected pin on
the XC3S400 that maps to a user-I/O pin on the XC3S1000,
XC3S1500, and XC3S2000. If the table entry is shaded tan,
then the unconnected pin on the XC3S400 maps to a
VREF-type pin on the XC3S1000, the XC3S1500, or the
XC3S2000. If the other VREF pins in the bank all connect to
a voltage reference to support a special I/O standard, then
also connect the N.C. pin on the XC3S400 to the same
VREF voltage. This provides maximum flexibility as you
could potentially migrate a design from the XC3S400 device
to an XC3S1000, an XC3S1500, or an XC3S2000 FPGA
without changing the printed circuit board.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web-
site at
Pinout Table
Table 99: FG456 Package Pinout
DS099-4 (v2.2) May 25, 2007
Product Specification
Bank
0
0
0
0
0
0
0
0
0
http://www.xilinx.com/bvdocs/publications/s3_pin.zip
48, these unconnected pins are indicated with a
and
IO
IO
IO
IO
IO/VREF_0
IO/VREF_0
N.C. ( )
IO/VREF_0
IO_L01N_0/
VRP_0
R
Pin Name
Figure
3S400
48. The XC3S400, however, has fewer
IO
IO
IO
IO
IO/VREF_0
IO/VREF_0
IO/VREF_0
IO/VREF_0
IO_L01N_0/
VRP_0
Pin Name
3S1000
3S1500
3S2000
Table 99
Table
Number
FG456
and are sorted by
A10
D10
Pin
D9
A3
C7
E5
B4
F6
F7
99. If the table
Table 99
VREF
VREF
VREF
VREF
Type
DCI
I/O
I/O
I/O
I/O
www.xilinx.com
and
.
Table 99: FG456 Package Pinout (Continued)
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
IO_L01P_0/
VRN_0
IO_L06N_0
IO_L06P_0
IO_L09N_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
N.C. ( )
N.C. ( )
N.C. ( )
N.C. ( )
IO_L24N_0
IO_L24P_0
IO_L25N_0
IO_L25P_0
IO_L27N_0
IO_L27P_0
IO_L28N_0
IO_L28P_0
IO_L29N_0
IO_L29P_0
IO_L30N_0
IO_L30P_0
IO_L31N_0
IO_L31P_0/
VREF_0
IO_L32N_0/
GCLK7
IO_L32P_0/
GCLK6
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
IO
IO
IO
IO
IO
IO
Spartan-3 FPGA Family: Pinout Descriptions
Pin Name
3S400
IO_L01P_0/
VRN_0
IO_L06N_0
IO_L06P_0
IO_L09N_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
IO_L19N_0
IO_L19P_0
IO_L22N_0
IO_L22P_0
IO_L24N_0
IO_L24P_0
IO_L25N_0
IO_L25P_0
IO_L27N_0
IO_L27P_0
IO_L28N_0
IO_L28P_0
IO_L29N_0
IO_L29P_0
IO_L30N_0
IO_L30P_0
IO_L31N_0
IO_L31P_0/
VREF_0
IO_L32N_0/
GCLK7
IO_L32P_0/
GCLK6
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
IO
IO
IO
IO
IO
IO
Pin Name
3S1000
3S1500
3S2000
Number
FG456
G10
E10
C10
B10
D11
C11
G11
A12
E16
F10
F11
E11
B11
A11
F12
F13
F16
F17
Pin
A4
D5
C5
B5
A5
E6
D6
C6
B6
E7
D7
B7
A7
E8
D8
B8
A8
E9
B9
A9
C8
G9
F9
F8
VCCO
VCCO
VCCO
VCCO
VCCO
GCLK
GCLK
VREF
Type
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
153