XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 110

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Spartan-3 FPGA Family: Pinout Descriptions
CCLK: Configuration Clock
The configuration clock signal on this pin synchronizes the
reading or writing of configuration data. The CCLK pin is an
input-only pin for the Slave Serial and Slave Parallel config-
uration modes. In the Master Serial and Master Parallel
configuration modes, the FPGA drives the CCLK pin and
CCLK should be treated as a full bidirectional I/O pin for sig-
nal integrity analysis.
Although the CCLK frequency is relatively low, Spartan-3
FPGA output edge rates are fast. Any potential signal integ-
rity problems on the CCLK board trace can cause FPGA
configuration to fail. Therefore, pay careful attention to the
CCLK signal integrity on the printed circuit board. Signal
integrity simulation with IBIS is recommended. For all con-
figuration modes except JTAG, consider the signal integrity
at every CCLK trace destination, including the FPGA’s
CCLK pin.
During configuration, the CCLK pin has a pull-up resistor to
VCCAUX, regardless of the HSWAP_EN pin. After configu-
ration, the CCLK pin is pulled High to VCCAUX by default
as defined by the CclkPin bitstream selection, although this
behavior is programmable. Any clocks applied to CCLK
after configuration are ignored unless the bitstream option
Persist is set to Yes, which retains the configuration inter-
face. Persist is set to No by default. However, if Persist is
set to Yes, then all clock edges are potentially active
events, depending on the other configuration control sig-
nals.
The bitstream generator option ConfigRate determines the
frequency of the internally-generated CCLK oscillator
required for the Master configuration modes. The actual fre-
quency is approximate due to the characteristics of the sili-
con oscillator and varies by up to 50% over the temperature
and voltage range. By default, CCLK operates at approxi-
mately 6 MHz. Via the ConfigRate option, the oscillator fre-
quency is set at approximately 3, 6, 12, 25, or 50 MHz. At
power-on, CCLK always starts operation at its lowest fre-
quency. The device does not start operating at the higher
frequency until the ConfigRate control bits are loaded dur-
ing the configuration process.
PROG_B: Program/Configure Device
This asynchronous pin initiates the configuration or re-con-
figuration processes. A Low-going pulse resets the configu-
ration logic, initializing the configuration memory. This
initialization process cannot finish until PROG_B returns
High. Asserting PROG_B Low for an extended period
delays the configuration process. At power-up, there is
always a pull-up resistor to VCCAUX on this pin, regardless
of the HSWAP_EN input. After configuration, the bitstream
generator option ProgPin determines whether or not the
pull-up resistor is present. By default, the ProgPin option
retains the pull-up resistor.
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After configuration, hold the PROG_B input High. Any
Low-going pulse on PROG_B, lasting 300 ns or longer,
restarts the configuration process.
Table 72: PROG_B Operation
DONE: Configuration Done, Delay Start-Up
Sequence
The FPGA produces a Low-to-High transition on this pin
indicating that the configuration process is complete. The
bitstream generator option DriveDone determines whether
this pin functions as a totem-pole output that can drive High
or as an open-drain output. If configured as an open-drain
output—which is the default behavior—then a pull-up resis-
tor is required to produce a High logic level. There is a bit-
stream option that provides an internal pull-up resistor,
otherwise an external pull-up resistor is required.
The open-drain option permits the DONE lines of multiple
FPGAs to be tied together, so that the common node transi-
tions High only after all of the FPGAs have completed con-
figuration. Externally holding the open-drain DONE pin Low
delays the start-up sequence, which marks the transition to
user mode.
Once the FPGA enters User mode after completing configura-
tion, the DONE pin no longer drives the DONE pin Low. The
bitstream generator option DonePin determines whether or
not a pull-up resistor is present on the DONE pin to pull the pin
to VCCAUX. If the pull-up resistor is eliminated, then the
DONE pin must be pulled High using an external pull-up resis-
tor or one of the FPGAs in the design must actively drive the
DONE pin High via the DriveDone bitstream generator option.
The bitstream generator option DriveDone causes the FPGA
to actively drive the DONE output High after configuration. This
option should only be used in single-FPGA designs or on the
last FPGA in a multi-FPGA daisy-chain.
By default, the bitstream generator software retains the pull-up
resistor and does not actively drive the DONE pin as high-
lighted in
stream options in single- and multi-FPGA designs.
Low-going pulse
PROG_B Input
Extended Low
Power-up
Table
1
73.
Table 73
Automatically initiates configuration
process.
Initiate (re-)configuration process and
continue to completion.
Initiate (re-)configuration process and
stall process at step where
configuration memory is cleared.
Process is stalled until PROG_B
returns High.
If the configuration process is started,
continue to completion. If
configuration process is complete,
stay in User mode.
shows the interaction of these bit-
DS099-4 (v2.2) May 25, 2007
Response
Product Specification
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