XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 79

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Simultaneously Switching Output Guidelines
This section provides guidelines for the maximum allowable
number of Simultaneous Switching Outputs (SSOs). These
guidelines describe the maximum number of user I/O pins,
of a given output signal standard, that should simulta-
neously switch in the same direction, while maintaining a
safe level of switching noise. Meeting these guidelines for
the stated test conditions ensures that the FPGA operates
free from the adverse effects of ground and power bounce.
Ground or power bounce occurs when a large number of
outputs simultaneously switch in the same direction. The
output drive transistors all conduct current to a common
voltage rail. Low-to-High transitions conduct to the V
rail; High-to-Low transitions conduct to the GND rail. The
resulting cumulative current transient induces a voltage dif-
ference across the inductance that exists between the die
pad and the power supply or ground return. The inductance
is associated with bonding wires, the package lead frame,
and any other signal routing inside the package. Other vari-
ables contribute to SSO noise levels, including stray induc-
tance on the PCB as well as capacitive loading at receivers.
Any SSO-induced voltage consequently affects internal
switching noise margins and ultimately signal quality.
Table 48
lines. For each device/package combination,
vides the number of equivalent V
Table 48: Equivalent V
DS099-3 (v2.2) May 25, 2007
Product Specification
98
Notes:
1. The V
2. The information in this table also applies to Pb-free packages.
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Device
pair of interconnected banks shares three V
and
CCO
R
Table 49
lines for the pair of banks on each side of the CP132 and TQ144 packages are internally tied together. Each
VQ100
1
1
-
-
-
-
-
-
provide the essential SSO guide-
CCO
CP132
1.5
/GND Pairs per Bank
-
-
-
-
-
-
-
(1)
CCO
TQ144
/GND pairs. For each
1.5
1.5
1.5
-
-
-
-
-
(1)
Table 48
CCO
PQ208
/GND pairs. Consequently, the per bank number is 1.5.
2
2
2
-
-
-
-
-
www.xilinx.com
CCO
pro-
Spartan-3 FPGA Family: DC and Switching Characteristics
FT256
output signal standard and drive strength,
mends the maximum number of SSOs, switching in the
same direction, allowed per V
bank. The
style. Multiply the appropriate numbers from
Table 49
allowed within an I/O bank. Exceeding these SSO guide-
lines may result in increased power or ground bounce,
degraded signal integrity, or increased system jitter.
The recommended maximum SSO values assume that the
FPGA is soldered on the printed circuit board and that the
board uses sound design practices. The SSO values do not
apply for FPGAs mounted in sockets, due to the lead induc-
tance introduced by the socket.
The number of SSOs allowed for quad-flat packages (VQ,
TQ, PQ) is lower than for ball grid array packages (FG) due
to the larger lead inductance of the quad-flat packages. The
results for chip-scale packaging (CP132) are better than
quad-flat packaging but not as high as for ball grid array
packaging. Ball grid array packages are recommended for
applications with a large number of simultaneously switch-
ing outputs.
3
3
3
-
-
-
-
-
FG320
SSO
to calculate the maximum number of SSOs
3
3
3
Table 49
-
-
-
-
-
MAX
/IO Bank =
FG456
guidelines are categorized by package
5
5
5
5
-
-
-
-
FG676
Table 48
CCO
5
6
6
6
-
-
-
-
/GND pair within an I/O
x
FG900
Table 49
10
10
Table 49
9
-
-
-
-
-
Table 48
FG1156
recom-
12
12
-
-
-
-
-
-
and
79