XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 15

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Pull-Up and Pull-Down Resistors
The optional pull-up and pull-down resistors are intended to
establish High and Low levels, respectively, at unused I/Os.
The pull-up resistor optionally connects each IOB pad to
V
GND. These resistors are placed in a design using the
PULLUP and PULLDOWN symbols in a schematic, respec-
tively. They can also be instantiated as components, set as
constraints or passed as attributes in HDL code. These
resistors can also be selected for all unused I/O using the
Bitstream Generator (BitGen) option UnusedPin. A Low
logic level on HSWAP_EN activates the pull-up resistors on
all I/Os during configuration.
The Spartan-3 I/O pull-up and pull-down resistors are signif-
icantly stronger than the "weak" pull-up/pull-down resistors
used in previous Xilinx FPGA families. See
page 58
Keeper Circuit
Each I/O has an optional keeper circuit that retains the last
logic level on a line after all drivers have been turned off.
This is useful to keep bus lines from floating when all con-
nected drivers are in a high-impedance state. This function
is placed in a design using the KEEPER symbol. Pull-up
and pull-down resistors override the keeper circuit.
ESD Protection
Clamp diodes protect all device pads against damage from
Electro-Static Discharge (ESD) as well as excessive voltage
DS099-2 (v2.2) May 25, 2007
Product Specification
CCO
. A pull-down resistor optionally connects each pad to
180˚ 0˚
DCM
for equivalent resistor strengths.
Figure 6: Clocking the DDR Register
R
D1
D2
CLK1
CLK2
Q1
Q2
DDR MUX
FDDR
DS099-2_02_070303
Table 32,
Q
www.xilinx.com
transients. Each I/O has two clamp diodes: One diode
extends P-to-N from the pad to V
extends N-to-P from the pad to GND. During operation,
these diodes are normally biased in the off state. These
clamp diodes are always connected to the pad, regardless
of the signal standard selected. The presence of diodes lim-
its the ability of Spartan-3 I/Os to tolerate high signal volt-
ages. The V
page 55
Slew Rate Control and Drive Strength
Two options, FAST and SLOW, control the output slew rate.
The FAST option supports output switching at a high rate.
The SLOW option reduces bus transients. These options are
only available when using one of the LVCMOS or LVTTL
standards, which also provide up to seven different levels of
current drive strength: 2, 4, 6, 8, 12, 16, and 24 mA. Choos-
ing the appropriate drive strength level is yet another means
to minimize bus transients.
Table 6
LVTTL standards support.
Table 6: Programmable Output Drive Current
Boundary-Scan Capability
All Spartan-3 IOBs support boundary-scan testing compati-
ble with IEEE 1149.1 standards. During boundary scan
operations such as EXTEST and HIGHZ the I/O pull-down
resistor is active. For more information, see
ary-Scan (JTAG) Mode, page
Boundary Scan and BSDL Files” chapter in UG331.
SelectIO Signal Standards
The IOBs support 18 different single-ended signal stan-
dards, as listed in
IOBs can be used in specific pairs supporting any of eight
differential signal standards, as shown in
To define the I/O signaling standard in a design, set the
IOSTANDARD attribute to the appropriate setting. Xilinx
provides a variety of different methods for applying the
IOSTANDARD for maximum flexibility. For a full description
of different methods of applying attributes to control
IOSTANDARD, refer to the “Using I/O Resources” chapter
in UG331.
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
(IOSTANDARD)
Standard
Signal
Spartan-3 FPGA Family: Functional Description
shows the drive strengths that the LVCMOS and
specifies the voltage range that I/Os can tolerate.
IN
absolute maximum rating in
2
Table
4
7. Furthermore, the majority of
Current Drive (mA)
6
49, and refer to the “Using
CCO
8
-
and a second diode
Table
12
-
8.
16
-
-
Table 27,
Bound-
24
-
-
-
15